Static random access memory (SRAM) with programmable resistive elements

• US 9,672,911 B2
• Filed: 08/25/2015
• Issued: 06/06/2017
• Est. Priority Date: 08/25/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Roy, Anirban, Sadd, Michael A.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LEBOEUF, JEROME LARRY
• Application Number:
  US14/835,363
• Publication Number:
  US 20170062049A1
• Time in Patent Office: 651 Days
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. The first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node. The second terminal of the first resistive element is coupled to a first source line voltage. The second terminal of the second resistive element is coupled to a second source line voltage. A first transistor includes a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node.

Claims

1. A memory device comprising:

a volatile memory cell; and

a non-volatile memory cell that includes;

a first resistive element having a first terminal and a second terminal;

a second resistive element having a first terminal and a second terminal, wherein

the first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node,

the second terminal of the first resistive element is coupled to a first source line voltage,

the second terminal of the second resistive element is coupled to a second source line voltage;

a first transistor having a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node; and

a second transistor including a first current electrode coupled to the first node, a second current electrode coupled to a non-volatile bit line, and a control electrode coupled to a non-volatile word line;

wherein data from the non-volatile memory cell is restored to the volatile memory cell when, after a “

1”

is written to the volatile memory cell, a read voltage is applied at the first source line while a first bias voltage is applied at the second source line and a second bias voltage is applied at the non-volatile word line.

2. The memory device of claim 1, wherein the volatile memory cell further comprises:

a first pass transistor having a first current electrode coupled to a true volatile bit line, a second current electrode coupled to the first data storage node, and a control electrode coupled to a volatile word line.

3. The memory device of claim 2, wherein the volatile memory cell further comprises:

a second pass transistor having a first current electrode coupled to a complementary volatile bit line, a second current electrode coupled to a second data storage node, and a control electrode coupled to the volatile word line.

4. The memory device of claim 3, further comprising:

a first inverter including an input coupled to the first data storage node and an output coupled to the second data storage node; and

a second inverter including an output coupled to the first data storage node and an input coupled to the second data storage node.

5. The memory device of claim 1, wherein the non-volatile memory cell is disabled when voltage on a nonvolatile wordline and the first and second source lines is set to ground.

6. The memory device of claim 1,

wherein the first bias voltage is less than the read voltage and the second bias voltage deactivates the second transistor.

7. The memory device of claim 1, wherein a “

1”

in the volatile memory cell is stored in the non-volatile memory cell when, after the second resistive element is programmed to a low resistance state while current at the non-volatile bit line is limited, the first resistive element is erased to a high resistance state while voltage at the non-volatile bit line is limited.

8. The memory device of claim 1, wherein a “

0”

in the volatile memory cell is stored in the non-volatile memory cell when, after the first resistive element is programmed to a low resistance state while current at the non-volatile bit line is limited, the second resistive element is erased to a high resistance state while voltage at the non-volatile bit line is limited.

9. The memory device of claim 1, wherein transistors in the volatile memory cell are low voltage transistors and the first and second transistors in the non-volatile memory cell are high voltage transistors.

10. The memory device of claim 1, wherein a resistance level of the first resistive element is programmable between a high resistance state and a low resistance state, and a resistance level of the second resistive element is programmable between another high resistance state and another low resistance state.

11. The memory device of claim 1, wherein the supply voltage comprises a ground supply voltage.

12. A method of operating a memory device comprising:

restoring data from a non-volatile memory cell to a volatile memory cell by;

writing a “

1”

into the volatile memory cell via a pass transistor having a first current electrode coupled to a volatile bit line, a second current electrode coupled to a data storage node of the volatile memory cell, and a control electrode coupled to a volatile word line;

after the writing the “

1”

into the volatile memory cell, applying a read voltage at a first source line coupled to a first terminal of a first programmable resistive element of the non-volatile memory cell, wherein

a second terminal of the first resistive element is coupled at a first node to a first terminal of a second programmable resistive element and a control electrode of a first transistor,

a second terminal of the second resistive element is coupled to a first bias voltage at a second source line that is less than the read voltage,

a first current electrode of the first transistor is coupled to the data storage node of the volatile memory cell, and

a second current electrode of the first transistor is coupled to a first supply voltage.

13. The method of claim 12, further comprising:

writing a “

0”

to the volatile memory cell when the first programmable resistive element is in a low resistance state, the second programmable resistive element is in a high resistance state, and voltage at the first node is high during restore.

14. The method of claim 12, further comprising:

writing a “

1”

to the volatile memory cell when the first programmable resistive element is in a high resistance state, the second programmable resistive element is in a low resistance state, and voltage at the first node is low during restore.

15. The method of claim 12, further comprising:

transferring a “

1”

in the volatile memory cell to the non-volatile memory cell by

programming the second programmable resistive element to a low resistance state while current at a non-volatile bit line is limited, and

erasing the first programmable resistive element to a high resistance state while voltage at the non-volatile bit line is limited;

transferring a “

0”

in the volatile memory cell to the non-volatile memory cell by

programming the first programmable resistive element to a low resistance state while current at the non-volatile bit line is limited, and

erasing the second programmable resistive element to a high resistance state while voltage at the non-volatile bit line is limited.

16. The method of claim 15, further comprising:

reading the data in the volatile memory cell and storing the data read from the volatile memory to a storage buffer before transferring the “

1”

or the “

0”

to the non-volatile memory.

17. The method of claim 12, further comprising:

while restoring the data, applying a second bias voltage at a non-volatile word line while the first bias voltage is applied at the second source line, wherein

the non-volatile word line is coupled to a control electrode of a second transistor in the non-volatile memory cell,

the second bias voltage deactivates the second transistor, and

the second transistor further includes a first current electrode coupled to the first node and a second current electrode coupled to a non-volatile bit line.

18. A processing system on a chip (SOC) comprising:

a processor on a semiconductor substrate; and

a memory device on the semiconductor substrate, the memory device is coupled to communicate with the processor and includes;

an array of volatile memory cells and corresponding non-volatile memory cells, wherein

each of the volatile memory cells includes;

a pass transistor having a first current electrode coupled to a volatile bit line, a second current electrode coupled to a data storage node, and a control electrode coupled to a volatile word line, and

each of the non-volatile memory cells includes;

a first programmable resistive element having a first terminal and a second terminal, wherein a resistance level of the first programmable resistive element varies between a high resistance state and a low resistance state;

a second programmable resistive element having a first terminal and a second terminal, wherein a resistance level of the second programmable resistive element varies between a high resistance state and a low resistance state,

the first terminal of the first programmable resistive element is coupled to the first terminal of the second resistive element at a first node,

the second terminal of the first programmable resistive element is coupled to a first source line voltage,

the second terminal of the second resistive element is coupled to a second source line voltage;

a first transistor having a first current electrode coupled to the data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node;

wherein data in one of the non-volatile memory cells is programmed into a corresponding one of the volatile memory cells when, after a “

1”

is written to the volatile memory cell, a read voltage is applied at the first source line while a first bias voltage is applied at the second source line and a second bias voltage is applied at a non-volatile word line.

19. The processing SOC of claim 18, wherein:

a “

1”

in one of the volatile memory cells is stored in a corresponding one of the non-volatile memory cells when the second resistive element is programmed to the low resistance state and the first resistive element is erased to the high resistance state;

a “

0”

in the one of the volatile memory cells is stored in the corresponding one of the non-volatile memory cells when the first resistive element is programmed to the low resistance state, the second resistive element is erased to the high resistance state.