Temperature compensation management in solid-state memory

• US 9,672,934 B2
• Filed: 02/25/2016
• Issued: 06/06/2017
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Stoev, Kroum S., Liang, Guirong, Li, Haibo, Zhao, Dengtao, Sun, Yongke
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/053,133
• Publication Number:
  US 20160172051A1
• Time in Patent Office: 467 Days
• Field of Search: 36518502, 36518503, 36518522, 36518524, 365211
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.

Claims

1. A data storage device comprising:

a non-volatile memory array including memory cells; and

a controller configured to;

determine a program/erase (P/E) cycling condition of at least a portion of the non-volatile memory array;

determine a first offset program verify level associated with a first programming level based at least in part on the P/E cycling condition;

determine a second offset program verify level associated with a second programming level based at least in part on the P/E cycling condition;

program a first set of the memory cells of the non-volatile memory array using the first offset program verify level; and

program a second set of the memory cells of the non-volatile memory array using the second offset program verify level;

wherein the first and second offset program verify levels are determined to provide more even distribution of programming levels, thereby reducing an overall bit error rate associated with the non-volatile memory array.

2. The data storage device of claim 1, wherein the controller is further configured to maintain a system table associating P/E cycle count values with program verify level offset values.

3. The data storage device of claim 2, wherein the controller is further configured to determine the first offset program verify level at least in part by referencing the system table.

4. The data storage device of claim 1, wherein said determining the first offset program verify level is based at least in part on a temperature associated with at least a portion of the data storage device.

5. The data storage device of claim 1, wherein said determining the first offset program verify level is based at least in part on a bit error rate associated with at least a portion of the non-volatile memory array.

6. The data storage device of claim 1, wherein the controller is further configured:

determine an offset voltage read level associated with the first programing level based at least in part on the P/E cycling condition; and

read a third set of the memory cells of the non-volatile memory array using the offset voltage read level.

7. A data storage device comprising:

a non-volatile memory array including memory cells; and

a controller configured to;

determine a bit error rate associated with at least a portion of the non-volatile memory array;

determine a first offset program verify level associated with a first programming level based at least in part on the bit error rate;

determine a second offset program verify level associated with a second programming level based at least in part on the bit error rate;

program a first set of the memory cells of the non-volatile memory array using the first offset program verify level; and

program a second set of the memory cells of the non-volatile memory array using the second offset program verify level;

wherein the first and second offset program verify levels are determined to provide more even distribution of programming levels.

8. The data storage device of claim 7, wherein the controller is further configured to maintain a system table associating bit error rate values with program verify level offset values.

9. The data storage device of claim 8, wherein the controller is further configured to determine the first offset program verify level at least in part by referencing the system table.

10. The data storage device of claim 7, wherein said determining the first offset program verify level is based at least in part on a program/erase (P/E) count associated with at least a portion of the non-volatile memory array.

11. The data storage device of claim 7, wherein said determining the first offset program verify level is based at least in part on a temperature associated with at least a portion of the data storage device.

12. The data storage device of claim 7, wherein the controller is further configured:

determine an offset voltage read level associated with the first programing level based at least in part on the bit error rate; and

read a third set of the memory cells of the non-volatile memory array using the offset voltage read level.

13. A data storage device comprising:

a non-volatile memory array including memory cells; and

a controller configured to;

determine a physical condition associated with at least a portion of the non-volatile memory array;

determine a first offset program verify level associated with a first programming level based at least in part on the physical condition, the first offset program verify level being greater than a first default program verify level associated with the first programming level by a first offset amount;

determine a second offset program verify level associated with a second programming level based at least in part on the physical condition, the second offset program verify level being greater than a second default program verify level associated with the second programming level by a second offset amount;

program a first set of the memory cells of the non-volatile memory array using the first offset program verify level; and

program a second set of the memory cells of the non-volatile memory array using the second offset program verify level;

wherein the first offset amount is greater than the second offset amount.

14. The data storage device of claim 13, wherein the physical condition is a temperature associated with at least a portion of the data storage device.

15. The data storage device of claim 13, wherein the physical condition is a program/erase (P/E) count associated with at least a portion of the non-volatile memory array.

16. The data storage device of claim 13, wherein the physical condition is a bit error rate associated with at least a portion of the non-volatile memory array.

17. The data storage device of claim 13, wherein the controller is further configured to maintain a system table associating physical condition values with program verify level offset values and determine the first offset program verify level at least in part by referencing the system table.

18. The data storage device of claim 13, wherein the first offset amount is greater than zero when a temperature of the data storage device is greater than or equal to a predetermined temperature threshold.

19. The data storage device of claim 18, wherein the predetermined temperature threshold is approximately 25°

C.

20. The data storage device of claim 13, wherein the controller is further configured:

determine an offset voltage read level associated with the first programing level based at least in part on the physical condition; and

read a third set of the memory cells of the non-volatile memory array using the offset voltage read level.