Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby

• US 9,673,102 B2
• Filed: 04/01/2011
• Issued: 06/06/2017
• Est. Priority Date: 04/01/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun, Tang, Sanh D., Wells, David H.
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Peterson, Erik T
• Application Number:
  US13/078,274
• Publication Number:
  US 20120248529A1
• Time in Patent Office: 2,258 Days
• Field of Search: 438102, 438270, 438589
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

Claims

1. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistors, the method comprising:

forming at least one trench in the periphery region of a substrate and at least one trench in the array portion of the substrate concurrently, the at least one trench in the periphery region producing one or more fins in the periphery region and the at least one trench in the array portion producing one or more fins in the array portion;

forming each of the peripheral circuit transistors over a fin of the one or more fins in the periphery region;

forming the plurality of vertical array transistors from the one or more fins in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and

forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors.

2. The method of claim 1, wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are within 500 Å

of average elevation.

3. The method of claim 1, wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are within 200 Å

of average elevation.

4. The method of claim 1, wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are coplanar.

6. The method of claim 1, wherein forming the phase change memory cells comprises:

depositing metal on the self-aligned contact of each of the vertical array transistors;

forming a recess in an upper surface of the deposited metal on each of the vertical array transistors; and

depositing a phase-change material over the deposited metal on each of the vertical array transistors.

5. The method of claim , wherein forming the phase change memory cells comprises:

forming a plurality of silicide contacts by silicidation of the self-aligned contact of each of the vertical array transistors; and

depositing a phase-change material over each of the plurality of silicide contacts.

7. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:

forming the peripheral circuit transistor structures in the periphery region;

forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and

forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,

wherein forming the plurality of vertical array transistors comprises;

doping an upper surface of a substrate in the array portion;

forming an oxide over the array portion and the periphery region, wherein the oxide extends above an upper surface of the peripheral circuit transistor structures;

forming a first plurality of trenches in the array portion, the first plurality of trenches extending through the oxide to the doped upper surface of the substrate;

growing epitaxial silicon within the first plurality of trenches;

forming a patterned resist material mask on the array portion, in a direction perpendicular to a direction of formation of the first plurality of trenches, and forming the resist material mask over the entire periphery region;

etching unmasked areas of the oxide and unmasked areas of the epitaxial silicon within the first plurality of trenches to form a second plurality of trenches, the second plurality of trenches extending through the oxide and epitaxial silicon to the doped upper surface of the substrate, resulting in a plurality of silicon pillars in the array portion;

removing the resist material;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and

forming side gates on the gate oxide.

8. The method of claim 7, wherein doping the upper surface of the substrate comprises an n-type doping.

9. The method of claim 7, wherein the oxide comprises silicon dioxide.

10. The method of claim 7, wherein forming the side gates comprises:

depositing a gate material on sides of the gate oxide covered silicon pillars; and

etching the gate material to be recessed below a top surface of the gate oxide covered silicon pillars.

11. The method of claim 10, wherein the gate material is TiN.

12. The method of claim 10, wherein depositing the gate material comprises atomic layer deposition and etching the gate material comprises a spacer etch process.

13. The method of claim 7, wherein forming the phase change memory cells comprises:

forming a plurality of silicide contacts by silicidation of the self-aligned contact of each of the vertical array transistors; and

depositing a phase-change material over each of the plurality of silicide contacts.

14. The method of claim 13, wherein the phase-change material comprises germanium, antimony, and tellurium.

15. The method of claim 7, wherein forming the phase change memory cells comprises:

depositing metal on the self-aligned contact of each of the vertical array transistors;

forming a recess in an upper surface of the deposited metal on each of the vertical array transistors; and

depositing a phase-change material over the deposited metal on each of the vertical array transistors.

16. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:

forming the peripheral circuit transistor structures in the periphery region;

forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and

forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,

wherein forming the plurality of vertical array transistors comprises;

doping an upper surface of a substrate in the array portion;

forming an oxide over the array portion and the periphery region, wherein the oxide extends above an upper surface of the peripheral circuit transistor structures;

forming a plurality of trenches through the oxide to the doped upper surface of the substrate;

growing epitaxial silicon within the plurality of trenches to form a plurality of silicon pillars;

etching the oxide to expose sides of the plurality of silicon pillars;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and

forming all around gates on the silicon pillars.

17. The method of claim 16, wherein forming the all around gates comprises:

depositing a gate material on the gate oxide; and

etching the gate material to be recessed below a top surface of the gate oxide.

18. The method of claim 17, wherein the gate material is TiN.

19. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:

forming the peripheral circuit transistor structures in the periphery region;

forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and

forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,

wherein forming the peripheral circuit transistor structures and forming the plurality of vertical array transistors comprises;

forming a pad oxide on a silicon substrate;

forming a nitride on the pad oxide;

forming at least one first trench in the periphery region, for formation of shallow trench isolation regions, and a plurality of second trenches in the array portion;

doping the silicon substrate in the periphery region for transistor structure formation;

doping the silicon substrate in the array portion;

depositing an oxide into the at least one first trench and the plurality of second trenches, and planarizing the oxide to a top surface of the nitride;

forming a patterned resist material mask on the array portion, in a direction perpendicular to a direction of formation of the plurality of second trenches, and forming the resist material mask over the entire periphery region;

etching unmasked areas of the array portion to form a plurality of third trenches, the plurality of third trenches extending through the nitride, and the pad oxide to the doped array portion of the silicon substrate, resulting in a plurality of silicon pillars in the array portion;

removing the resist material;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the silicon substrate;

forming gates on the silicon pillars;

removing the nitride and the pad oxide from the periphery region; and

forming the self-aligned contacts by removing the nitride and the pad oxide from the array portion.

20. The method of claim 19, wherein forming the gates comprises:

depositing a gate material on sides of the gate oxide formed on the silicon pillars; and

etching the gate material to be recessed below a top surface of the silicon pillars, thereby forming the gates.

21. The method of claim 19, wherein the gates comprise TiN.

22. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:

forming the peripheral circuit transistor structures in the periphery region;

forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and

forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,

wherein forming the peripheral circuit transistor structures and forming the plurality of vertical array transistors comprises;

forming shallow trench isolation regions in a substrate in the periphery region;

forming a gate oxide;

forming a gate stack over the gate oxide in the periphery region;

forming a nitride spacer on a side surface of the gate stack between the periphery region and the array portion;

doping an upper surface of the substrate in the array portion;

growing epitaxial silicon in the array portion, wherein the epitaxial silicon is grown to a level of an upper surface of the gate stack;

forming a nitride cap over the array portion and the periphery region;

forming at least one transistor structure in the periphery region;

patterning the epitaxial silicon in the array portion;

forming a gate oxide on exposed surfaces of the epitaxial silicon;

forming gates;

depositing an oxide to gap fill the array portion and planarizing the oxide to the nitride cap; and

forming the self-aligned contacts for the plurality of vertical array transistors.

23. The method of claim 22, wherein forming the at least one transistor structure comprises:

forming a dummy hedge between the periphery region and the array portion.

24. The method of claim 22, wherein forming the gate stack comprises:

forming a polysilicon in the periphery region and array portion;

forming a metal in the periphery region and array portion;

forming a nitride in the periphery region and array portion; and

etching the polysilicon, metal, and nitride to remove the polysilicon, metal, and nitride from above the array portion, stopping on the gate oxide.

25. The method of claim 22, wherein patterning the epitaxial silicon in the array portion comprises:

forming a first plurality of trenches through the nitride and the epitaxial silicon;

depositing an oxide material for gap filling the first plurality of trenches and covering the peripheral circuit transistor structures;

forming a second plurality of trenches through the deposited oxide material, the nitride and the epitaxial silicon, the second plurality of trenches arranged perpendicularly to the first plurality of trenches; and

removing the oxide material from above the nitride.

26. The method of claim 25, further comprising:

removing the oxide material from between silicon pillars formed by the first plurality of trenches and the second plurality of trenches.

27. The method of claim 26, wherein forming the gates comprises:

depositing a gate material in spaces between the silicon pillars; and

spacer etching the gate material to be recessed below a surface of the silicon pillars.

28. The method of claim 26, wherein forming the plurality of self-aligned contacts comprises:

forming an oxide cap over the peripheral circuit transistor structures;

removing the nitride cap from above the silicon pillars; and

doping an upper surface of the silicon pillars.

29. The method of claim 25, wherein forming the gates comprises:

depositing a gate material in the second plurality of trenches; and

spacer etching the gate material to be recessed below a surface of the epitaxial silicon.