On chip electrostatic discharge (ESD) event monitoring

• US 9,673,116 B2
• Filed: 01/04/2013
• Issued: 06/06/2017
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DeForge, John B., Li, Junjun, Loiseau, Alain F., Peterson, Kirk D.
• Primary Examiner(s): MILLER, DANIEL R
• Application Number:
  US13/733,954
• Publication Number:
  US 20140191778A1
• Time in Patent Office: 1,614 Days
• Field of Search: 324457, 324537, 3247503, 32476202
• CPC Class Codes: G01R 31/002 where the device under test is an electronic circuit
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure.

Claims

1. A circuit structure for monitoring an electrostatic discharge (ESD) event in a manufacturing environment of an integrated circuit package, the circuit structure comprising:

a canary device for exhibiting an impedance shift when affected by an ESD pulse of the ESD event,

wherein a circuit drain of the canary device is connected to an input terminal of the circuit structure; and

wherein a circuit source and a logic gate of the canary device are connected to a circuit drain of an ESD transistor of the circuit structure, wherein a circuit source of the ESD transistor is connected to an output terminal of the circuit structure, wherein a logic gate of the ESD transistor is connected to an enable line of the circuit structure, and wherein the canary device is connected in series with one or more diodes of the circuit structure.

2. The circuit structure according to claim 1, wherein the circuit structure comprises multiple canary devices for monitoring the ESD event in the integrated circuit package.

3. The circuit structure according to claim 1, wherein the integrated circuit includes any memory storage.

4. The circuit structure according to claim 1 further comprising a power clamp.

5. The circuit structure according to claim 4, wherein the power clamp is an ESD structure that is used to create current discharge path during an ESD event between input and output terminal of the circuit structure.

6. The circuit structure according to claim 1, wherein the circuit structure amplifies leakage of current to the canary device, and wherein the leaked current is amplified to ensure that an input terminal of the integrated circuit loses functionality when the leaked current flows through the canary device.

7. A method for monitoring electrostatic discharge (ESD) event in a manufacturing environment of an integrated circuit package, the method comprising:

exhibiting an impedance shift when affected by an ESD pulse of the ESD event of a canary device of a circuit structure, wherein a circuit drain of the canary device is connected to an input terminal of the circuit structure, and wherein a circuit source and a logic gate of the canary device are connected to a circuit drain of an ESD transistor of the circuit structure, wherein a circuit source of the ESD transistor is connected to an output terminal of the circuit structure, wherein a logic gate of the ESD transistor is connected to an enable line of the circuit structure, wherein the canary device is connected in series with one or more diodes of the circuit structure.

8. The method according to claim 7, wherein the circuit structure comprises multiple canary devices for monitoring the ESD event in the integrated circuit package.

9. The method according to claim 7, wherein the integrated circuit includes any memory storage.

10. The method according to claim 7, further comprising a power clamp.

11. The circuit structure according to claim 10, wherein the power clamp is an ESD structure that is used to create current discharge path during an ESD event between input and output terminal of the circuit structure.

12. The method according to claim 7, wherein the circuit structure amplifies leakage of current to the canary device, and wherein the leaked current is amplified to ensure that an input terminal of the integrated circuit loses functionality when the leaked current flows through the canary device.