Bonded structures for package and substrate

• US 9,673,161 B2
• Filed: 07/18/2016
• Issued: 06/06/2017
• Est. Priority Date: 08/17/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Yao-Chun, Chen, Chen-Shien, Cha, Ming-Hong, Chuang, Chita, Chiang, Tsung-Hsien, Liu, Hao-Juin, Kuo, Chen-Cheng
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US15/212,970
• Publication Number:
  US 20160329293A1
• Time in Patent Office: 323 Days
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/1301 Shape
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13564 : Only on the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13601 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/141 : Disposition
• CPC Class Codes: H01L 2224/14134 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14152 : being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/14154 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14177 : Combinations of arrays with different layouts
• CPC Class Codes: H01L 2224/145 : Material
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/16505 : outside the bonding interface, e.g. in the bulk of the bump connector
• CPC Class Codes: H01L 2224/17051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/171 : Disposition
• CPC Class Codes: H01L 2224/17104 : relative to the bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/81143 : Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81194 : Lateral distribution of the bump connectors
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3841 : Solder bridging

Abstract

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Claims

1. A method of manufacturing a semiconductor device comprising:

receiving a first contact post on a first substrate, wherein the first contact post has a first elongated shape, a first sidewall, and a second sidewall opposite the first sidewall; and

receiving a passivation layer over a second substrate, the passivation layer comprising an opening that exposes a conductive region, the opening having a third sidewall and a fourth sidewall opposite the third sidewall, wherein the third sidewall and the fourth sidewall enclose a central region; and

electrically connecting the first contact post and the conductive region, wherein after the electrically connecting the first contact post and the conductive region the first sidewall is directly over the central region and the second sidewall is offset from the central region in a direction parallel with a major surface of the first substrate.

2. The method of claim 1, wherein the first contact post is part of a first plurality of contact posts, where each contact post within the first plurality of contact posts has the first elongated shape and are aligned in a first direction.

3. The method of claim 2, wherein the first direction is aligned with a center of the semiconductor device.

4. The method of claim 3, further comprising a second plurality of contact posts, where each contact post within the second plurality of contact posts has the first elongated shape and is aligned in a second direction different from the first direction, wherein the second direction is aligned with the center of the semiconductor device.

5. The method of claim 4, wherein the first plurality of contact posts and the second plurality of contact posts are located along an edge of the semiconductor device.

6. The method of claim 3, further comprising:

a first solder material in physical connection with the first contact post; and

a second solder material in physical connection with a second contact post, the second contact post being one of the first plurality of contact posts, wherein the first contact post and the second contact post are neighbors to each other and wherein the first solder material has a first widest point and the second solder material has a second widest point that is misaligned from the first widest point.

7. The method of claim 3, wherein the first contact post has a first surface facing the center and a second surface facing away from the center, wherein the second surface is wetted by solder and the first surface is free from solder.

8. A semiconductor device comprising:

a first semiconductor device bonded to a second semiconductor device, wherein a first line extends between a center of the first semiconductor device to a corner of the first semiconductor device;

a first contact of the first semiconductor device in electrical connection with a first contact pad of the second semiconductor device, wherein the first contact is located along the first line and has a first offset from the first contact pad; and

a second contact of the first semiconductor device in electrical connection with a second contact pad of the second semiconductor device, wherein the second contact is located along the first line and has a second offset from the second contact pad that is larger than the first offset, the second contact being located further from the center of the first semiconductor device than the first contact.

9. The semiconductor device of claim 8, wherein the second contact has a first sidewall and a second sidewall opposite the first sidewall, the first sidewall being located over the second contact pad and the second sidewall being located laterally removed from the second contact pad.

10. The semiconductor device of claim 8, wherein the second contact has a first sidewall and a second sidewall opposite the first sidewall, the first sidewall being wetted by solder and the second sidewall being free from solder, the second sidewall facing a center of the second semiconductor device.

11. The semiconductor device of claim 8, wherein the second contact is part of a first plurality of contacts, wherein each of the first plurality of contacts has an elongated shape with an axis and all of the axes of the first plurality of contacts are parallel.

12. The semiconductor device of claim 11, further comprising a second plurality of contact adjacent to the first plurality of contacts, wherein each of the second plurality of contacts has an elongated shape with an axis and all of the axes of the second plurality of contacts are parallel with each other and not parallel with the axes of the first plurality of contacts.

13. The semiconductor device of claim 11, wherein the second contact has a first sidewall and a second sidewall opposite the first sidewall, the first sidewall being wetted by solder and the second sidewall being free from solder, the second sidewall facing a center of the second semiconductor device.

14. The semiconductor device of claim 8, further comprising a passivation layer at least partially between the second contact and the second contact pad.

15. A semiconductor device comprising:

a semiconductor substrate with a center region and an edge region surrounding the center region;

a first plurality of bonded structures over the semiconductor substrate and located within the center region, each of the first plurality of bonded structures having a respective first axis, each of the respective first axes being parallel; and

a second plurality of bonded structures over the semiconductor substrate and located within the edge region, each of the second plurality of bonded structures having a respective second axis, each of the respective second axes being parallel, wherein the respective first axes are misaligned with the respective second axes and wherein each of the second plurality of bonded structures has a widest area that is not aligned with that of a neighboring one of the second plurality of bonded structures.

16. The semiconductor device of claim 15, wherein the widest areas are defined by a solder material.

17. The semiconductor device of claim 15, wherein a line extends from a first surface of a first one of the second plurality of bonded structures to a second surface of a second one of the second plurality of bonded structures, the first surface and the second surface facing a same direction, the line also intersecting the respective second axis of the first one of the second plurality of bonded structures at an angle of between about 30°

to about 60° and

also intersecting the respective second axis of the second one of the second plurality of bonded structures.

18. The semiconductor device of claim 17, wherein a space between neighboring bonded structures is from about 10 μ

m to about 130 μ

m.

19. The semiconductor device of claim 15, wherein each of the first plurality of bonded structures comprises a copper pillar with a first offset from a contact pad, wherein each of the second plurality of bonded structures comprises a copper pillar with a second offset from a contact pad, the second offset being greater than the first offset.

20. The semiconductor device of claim 15, wherein a first side of a first one of the second plurality of bonded structures is unwetted by solder while a second side of the first one of the second plurality of bonded structures is wetter by solder, the first side facing towards a center of the semiconductor substrate in a top down view.