Semiconductor device

• US 9,673,214 B2
• Filed: 03/16/2016
• Issued: 06/06/2017
• Est. Priority Date: 10/07/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hatano, Masaaki, Matsuura, Osamu
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US15/071,463
• Publication Number:
  US 20170103995A1
• Time in Patent Office: 447 Days
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.

Claims

1. A semiconductor device comprising:

an element region disposed on a substrate, semiconductor elements being collocated in the element region; and

a peripheral region disposed on the substrate, the peripheral region surrounding the element region, wherein

the element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate,

the peripheral region includes a peripheral layer arranged to surround the element region,

the peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction,

the first part and the second part have mutually different cross-section structures,

the first part is constituted of a second material having an internal stress with an opposite sign to an internal stress of a first material constituting the wiring layer, and

the second part is constituted of a third material having an internal stress with an identical sign to the internal stress of the first material.

2. The semiconductor device according to claim 1, wherein

the second part has a larger cross-sectional area in the cross-section structure than the first part.

3. The semiconductor device according to claim 1, wherein

the second part has a higher arrangement density than the first part.

4. The semiconductor device according to claim 1, wherein

the third material is a material identical to the first material.

5. The semiconductor device according to claim 1, wherein

the second material is titanium nitride (TiN) or titanium nitride aluminum (TiAlN).

6. The semiconductor device according to claim 5, wherein

the first material and the third material are tungsten.

7. The semiconductor device according to claim 1, wherein

the plurality of wiring layers are collocated on the substrate with interlayer insulating films therebetween.

8. The semiconductor device according to claim 7, wherein

the second part has a larger cross-sectional area in the cross-section structure than the first part.

9. The semiconductor device according to claim 7, wherein

the second part has a higher arrangement density than the first part.

10. The semiconductor device according to claim 7, further comprising:

a memory layer disposed on a side surface of the plurality of wiring layers and the interlayer insulating films, and

a semiconductor layer facing to the plurality of wiring layers across the memory layer.

11. The semiconductor device according to claim 1, further comprising:

an isolation insulating film disposed on the substrate, wherein

the peripheral layer has a lower end in contact with the isolation insulating film.

12. The semiconductor device according to claim 1, wherein

the peripheral layer is a guard ring for preventing water from invading from outside.

13. The semiconductor device according to claim 1, wherein

the peripheral layer is disposed in a dicing region for dicing memory chips.