Semiconductor device

• US 9,673,234 B2
• Filed: 05/11/2016
• Issued: 06/06/2017
• Est. Priority Date: 12/12/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Okazaki, Kenichi, Yamazaki, Shunpei, Katayama, Masahiro
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US15/151,539
• Publication Number:
  US 20160254291A1
• Time in Patent Office: 391 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76861 Post-treatment or after-treatment not introducing additional chemical elements into the layer
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10K 59/121 : characterised by the geometry or disposition of pixel elements

Abstract

A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The semiconductor device includes first to third transistors with different device structures over one substrate. A semiconductor layer of the first transistor is an oxide semiconductor film with a stacked-layer structure, and a semiconductor layer of each of the second and third transistors is an oxide semiconductor film with a single-layer structure. Each of the first and second transistors includes a back gate electrode connected to its gate electrode.

Claims

1. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising;

a first gate electrode;

a first insulating layer over the first gate electrode;

a first oxide semiconductor film over the first gate electrode with the first insulating layer interposed therebetween, the first oxide semiconductor film comprising a first channel formation region;

a second oxide semiconductor film on the first semiconductor film;

a second insulating layer over the second oxide semiconductor film;

a second gate electrode over the second oxide semiconductor film with the second insulating layer interposed therebetween; and

a first source electrode and a first drain electrode, wherein each of the first source electrode and the first drain electrode is in contact with the second oxide semiconductor film, and

a second transistor over the substrate, the second transistor comprising;

a third oxide semiconductor film over and in contact with the first insulating layer, the third oxide semiconductor film comprising a second channel formation region; and

a third insulating layer over and in contact with the third oxide semiconductor film,

wherein each of the first oxide film, the second oxide semiconductor film and the third oxide semiconductor film comprises indium and a second metal element different from indium, and

wherein an atomic ratio of indium in the first oxide semiconductor film is larger than an atomic ratio of indium in the second oxide semiconductor film and an atomic ratio of indium in the third oxide semiconductor film.

2. The semiconductor device according to claim 1,

wherein the atomic ratio of indium in the second oxide semiconductor film is the same as the atomic ratio of indium in the third oxide semiconductor film.

3. The semiconductor device according to claim 1,

wherein a top surface and a side surface of the first oxide semiconductor film are covered with the second oxide semiconductor film.

4. The semiconductor device according to claim 1,

wherein a field-effect mobility of the first transistor is greater than a field-effect mobility of the second transistor.

5. The semiconductor device according to claim 1,

wherein the second metal element is Zn, Al, Ga, Y, Zr, La, Ce, or Nd.

6. The semiconductor device according to claim 1,

wherein the first semiconductor film comprises In M₁-Zn oxide,

wherein M₁ is Al, Ga, Y, Zr, La, Ce, or Nd, and

wherein the second semiconductor film and the third semiconductor film comprises In-M₂-Zn oxide,

wherein M₂ is Al, Ga, Y, Zr, La, Ce, or Nd.

7. The semiconductor device according to claim 1,

wherein the second oxide semiconductor film and the third oxide semiconductor film are formed by patterning a same semiconductor film.

8. The semiconductor device according to claim 1,

wherein the second semiconductor film comprises a c-axis aligned crystalline oxide semiconductor.

9. The semiconductor device according to claim 1, further comprising a pixel electrode and a driver circuit for driving the pixel electrode,

wherein the second transistor is electrically connected to the pixel electrode, and

wherein the driver circuit comprises first transistor.

15. The semiconductor device according to claim 1,

wherein the first semiconductor film comprises In M₁-Zn oxide,

wherein M₁ is Al, Ga, Y, Zr, La, Ce, or Nd,

wherein the second semiconductor film comprises In-M₂-Zn oxide,

wherein M₂ is Al, Ga, Y, Zr, La, Ce, or Nd

wherein the third semiconductor film and the fourth semiconductor film comprises In-M₃-Zn oxide,

wherein M₃ is Al, Ga, Y, Zr, La, Ce, or Nd.

10. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising;

a first gate electrode;

a first insulating layer over the first gate electrode;

a first oxide semiconductor film over the first gate electrode with the first insulating layer interposed therebetween, the first oxide semiconductor film comprising a first channel formation region;

a second oxide semiconductor film on the first semiconductor film;

a third oxide semiconductor film on the second semiconductor film;

a second insulating layer over the third oxide semiconductor film;

a second gate electrode over the third oxide semiconductor film with the second insulating layer interposed therebetween; and

a first source electrode and a first drain electrode, wherein each of the first source electrode and the first drain electrode is in contact with the third oxide semiconductor film, and

a second transistor over the substrate, the second transistor comprising;

a fourth oxide semiconductor film over and in contact with the first insulating layer, the fourth oxide semiconductor film comprising a second channel formation region; and

a third insulating layer over and in contact with the fourth oxide semiconductor film,

wherein each of the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film comprises indium and a second metal element different from indium, and

wherein an atomic ratio of indium in the second oxide semiconductor film is larger than an atomic ratio of indium in the first oxide semiconductor film, an atomic ratio of indium in the third oxide semiconductor film, and an atomic ratio of indium in the fourth oxide semiconductor film.

11. The semiconductor device according to claim 10,

wherein the atomic ratio of indium in the third oxide semiconductor film is the same as the atomic ratio of indium in the fourth oxide semiconductor film.

12. The semiconductor device according to claim 10,

wherein a top surface and a side surface of the second oxide semiconductor film are covered with the third oxide semiconductor film,

wherein a side surface of the first oxide semiconductor film are covered with the third oxide semiconductor film.

13. The semiconductor device according to claim 10,

wherein a field-effect mobility of the first transistor is greater than a field-effect mobility of the second transistor.

14. The semiconductor device according to claim 10,

wherein the second metal element is Zn, Al, Ga, Y, Zr, La, Ce, or Nd.

16. The semiconductor device according to claim 10,

wherein the third oxide semiconductor film and the fourth oxide semiconductor film are formed by patterning a same semiconductor film.

17. The semiconductor device according to claim 10,

wherein the third semiconductor film comprises a c-axis aligned crystalline oxide semiconductor.

18. The semiconductor device according to claim 10 further comprising a pixel electrode and a driver circuit for driving the pixel electrode,

wherein the second transistor is electrically connected to the pixel electrode, and

wherein the driver circuit comprises first transistor.