Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits

• US 9,673,275 B2
• Filed: 10/22/2015
• Issued: 06/06/2017
• Est. Priority Date: 10/22/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Daeik Daniel, Yun, Changhan Hobie, Lan, Je-Hsiung Jeffrey, Mudakatte, Niranjan Sunil, Kim, Jonghae, Nowak, Matthew Michael
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/920,851
• Publication Number:
  US 20170117358A1
• Time in Patent Office: 593 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 29/0653 : adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

Claims

1. A radio-frequency (RF) circuit, comprising:

a plurality of complementary metal-oxide semiconductor (CMOS) devices;

a silicon substrate having doped regions that define the plurality of CMOS devices;

a trench through the silicon substrate that forms a continuous channel around the doped regions of a CMOS device among the plurality of CMOS devices to electrically isolate the CMOS device from at least one other CMOS device among the plurality of CMOS devices embodied on the silicon substrate;

a redistribution layer coupled to the silicon substrate; and

a via oriented along the trench that electrically connects one terminal of a plurality of terminals of the CMOS device to the redistribution layer.

2. The RF circuit of claim 1, wherein the redistribution layer is coupled to the silicon substrate via a layer of dielectric and without an interposed layer of buried oxide or trap-rich silicon.

3. The RF circuit of claim 2, wherein a length of the via includes a range of approximately three (3) micrometers to approximately five (5) micrometers.

4. The RF circuit of claim 1, wherein a thickness of the silicon substrate includes a range of approximately one (1) micrometer to approximately three (3) micrometers.

5. The RF circuit of claim 1, wherein the CMOS device comprises a direct contact device or body contact device that does not have a floating body.

6. The RF circuit of claim 1, wherein the trench comprises a first trench, the CMOS device comprises a first CMOS device, the continuous channel comprises a first continuous channel, and further comprising:

a second trench through the silicon substrate that forms a second continuous channel around the doped regions of a second CMOS device to electrically isolate the second CMOS device from the first CMOS device and the at least one other CMOS device on the silicon substrate.

7. The RF circuit of claim 1, wherein a width of the CMOS device across the silicon substrate is approximately twenty (20) micrometers to approximately forty (40) micrometers.

8. The RF circuit of claim 1, wherein an aspect ratio of a height of the trench divided by a width of the trench includes a range of approximately 0.3 to approximately 1.5.

9. The RF circuit of claim 1, wherein the continuous channel around the doped regions of the CMOS device is filled with an insulator.

10. The RF circuit of claim 1, wherein the continuous channel around the doped regions of the CMOS device completely separates the silicon substrate of the CMOS device from portions of the silicon substrate supporting the at least one other CMOS device.

11. The RF circuit of claim 1, wherein the silicon substrate is homogeneous and not coupled with an insulative substrate layer or a resistive substrate layer.

12. The RF circuit of claim 1, wherein a structure of the RF circuit is covered with a passivation layer and a top-molding layer, the passivation layer configured to support the top-molding layer.

13. The RF circuit of claim 1, wherein the CMOS device is configured in whole or in part as an RF switch or RF power amplifier.

14. The RF circuit of claim 1, wherein the RF circuit is implemented within a device configured as a modem, cellular base station, broadband router, access point, cellular phone, smart-phone, gaming device, navigation device, media device, laptop computer, desktop computer, server, network-attached storage (NAS) device, smart appliance, or vehicle-based communication system.

15. A radio-frequency (RF) circuit, comprising:

a silicon substrate;

a plurality of complementary metal-oxide semiconductor (CMOS) devices embodied on the silicon substrate;

means for electrically isolating a portion of the silicon substrate on which a CMOS device among the plurality of CMOS devices is electrically isolated from another portion of the silicon substrate on which at least one other CMOS device among the plurality of CMOS devices is embodied;

means for coupling a redistribution layer to the silicon substrate; and

means for electrically connecting, oriented along the means for electrically isolating the portion of the silicon substrate, a terminal of a plurality of terminals of the CMOS device to the redistribution layer.

16. The RF circuit of claim 15, wherein the means for coupling the redistribution layer to the silicon substrate comprises a layer of dielectric.

17. A radio-frequency (RF) semiconductor component, comprising:

a plurality of complementary metal-oxide semiconductor (CMOS) devices embodied on a silicon substrate, at least one CMOS device among the plurality of CMOS devices embodied on a portion of the silicon substrate that is separated from a remaining portion of the silicon substrate by a trench through the silicon substrate and around the at least one CMOS device;

a redistribution layer coupled to the silicon substrate that enables connectivity to the plurality of CMOS devices;

a via oriented along the trench that electrically connects one terminal of a plurality of terminals of the at least one CMOS device to the redistribution layer; and

an overmolding that encapsulates the plurality of CMOS devices and supports the redistribution layer.

18. The RF semiconductor component of claim 17, wherein the RF semiconductor component is configured as a switch or an amplifier.