Semiconductor device having modified profile metal gate
First Claim
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1. A semiconductor device, comprising:
- a semiconductor substrate having a top surface; and
a gate structure disposed over the semiconductor substrate, wherein the gate structure includes;
a first layer of a substantially U-shaped configuration and extending to a first height above the top surface;
a second layer having a substantially U-shaped configuration and extending to a second height above the top surface;
a third layer having a substantially U-shaped configuration and extending to a third height above the top surface, wherein each of the first, second and third heights are different, and wherein the first height is less than at least one of the second and third heights;
a fill layer disposed on the first, second and third layers wherein a top surface of the fill layer is disposed at a fourth height from the top surface of the semiconductor substrate, wherein the fourth height is greater than the first, second and third heights;
sidewall spacers disposed adjacent the gate structure, wherein the sidewall spacers extend to the fourth height.
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Abstract
A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
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19 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate having a top surface; and a gate structure disposed over the semiconductor substrate, wherein the gate structure includes; a first layer of a substantially U-shaped configuration and extending to a first height above the top surface; a second layer having a substantially U-shaped configuration and extending to a second height above the top surface; a third layer having a substantially U-shaped configuration and extending to a third height above the top surface, wherein each of the first, second and third heights are different, and wherein the first height is less than at least one of the second and third heights; a fill layer disposed on the first, second and third layers wherein a top surface of the fill layer is disposed at a fourth height from the top surface of the semiconductor substrate, wherein the fourth height is greater than the first, second and third heights; sidewall spacers disposed adjacent the gate structure, wherein the sidewall spacers extend to the fourth height. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
a gate structure having; an interfacial layer with a bottom portion and two side portions extending vertically above the bottom portion to a first height; a gate dielectric layer over the interfacial layer and having a bottom portion and two side portions extending vertically above the bottom portion to a second height; a metal work function layer over the interfacial layer and having a bottom portion and two side portions extending vertically above the bottom portion to a third height, wherein each of the two side portions are defined by a first and a second opposing sidewall; and a fill metal layer disposed over the metal work function layer and interfacing the first and second opposing sidewalls of each of the two side portions of the metal work function layer, and wherein each of the first, second and third heights are different. - View Dependent Claims (17, 18, 19)
Specification