Vertical power MOSFET and methods of forming the same

• US 9,673,297 B2
• Filed: 10/31/2014
• Issued: 06/06/2017
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Hsueh-Liang, Su, Po-Chih, Ng, Chun-Wai, Liu, Ruey-Hsin
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US14/530,246
• Publication Number:
  US 20150056770A1
• Time in Patent Office: 949 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.

Claims

1. A method comprising:

forming a gate dielectric layer over a body layer, wherein the body layer is over a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space, wherein during the implantation, an implanted impurity penetrates through the body layer, so that the doped semiconductor region reaches the semiconductor layer;

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode;

forming a dielectric layer covering the first gate electrode and the second gate electrode;

forming a field plate over the dielectric layer, wherein the field plate comprises;

a first portion overlapping the first gate electrode;

a second portion over the second gate electrode; and

a third portion in the space, wherein the third portion has a bottom surface physically contacting a top surface of a portion of the gate dielectric layer in the space;

etching a portion of the body layer to expose a sidewall of one of the heavily doped regions;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region, wherein an edge of the source region contacts the sidewall of the one of the heavily doped regions;

forming an inter-layer dielectric between the field plate and the source region; and

forming a drain region underlying the semiconductor layer.

2. The method of claim 1, wherein the gate dielectric layer extends into the space, and the implanting is performed with an implanted impurity penetrating through a portion of the gate dielectric layer in the space.

3. The method of claim 1, wherein the heavily doped regions are of the first conductivity type.

4. The method of claim 1, wherein the source region comprises a metal, and the source region is in contact with the sidewall of the one of the heavily doped regions.

5. The method of claim 1, wherein the source region comprises a portion filled into the space, with the portion level with the first gate electrode and the second gate electrode.

6. The method of claim 1, wherein the doped semiconductor region penetrates through the body layer to contact the semiconductor layer.

7. The method of claim 1, wherein

the first portion, the second portion, and the third portion are physically connected to form an integral region, and wherein the inter-layer dielectric separates the integral region from a portion of the source region overlapping the integral region.

8. The method of claim 1, wherein the first portion, the second portion, and the third portion are physically connected to form an integral region.

9. A method comprising:

epitaxially growing an epitaxy semiconductor layer of a first conductivity type;

epitaxially growing a body layer over the epitaxy semiconductor layer, wherein the body layer is of a second conductivity type opposite the first conductivity type;

forming a gate dielectric layer over the body layer;

forming a first and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space, and the doped semiconductor region extends to contact the epitaxy semiconductor layer;

after the doped semiconductor region is formed, forming a dielectric layer over the first and the second gate electrodes;

forming a conductive field plate over the dielectric layer, wherein the conductive field plate extends into the space between the first and the second gate electrodes, wherein the conductive field plate comprises a first portion overlapping the first gate electrode, a second portion over the second gate electrode, and a third portion in the space, and the first portion, the second portion, and the third portion are connected to form an integral region, wherein a portion of the gate dielectric layer in the space separates the third portion of the conductive field plate from the doped semiconductor region;

forming an inter-layer dielectric over the conductive field plate;

forming a source region comprising a portion overlapping the inter-layer dielectric and the conductive field plate; and

forming a drain region underlying the epitaxy semiconductor layer.

10. The method of claim 9, wherein the implanting the portion of the body layer is performed using the first and the second gate electrodes as a portion of an implantation mask.

11. The method of claim 9 further comprising forming a heavily doped semiconductor region of the first conductivity type, wherein the heavily doped semiconductor region and the doped semiconductor region are on opposite sides of a portion of the body layer that is overlapped by the first gate electrode.

12. The method of claim 9 further comprising:

after the doped semiconductor region is formed, forming a dielectric layer over the first and the second gate electrodes; and

etching the dielectric layer to form a contact opening, wherein a top surface of the body layer is exposed, and the source region comprises a first portion filled into the contact opening.

13. The method of claim 9, wherein the doped semiconductor region is implanted to have an impurity concentration higher than an impurity concentration of the epitaxy semiconductor layer.

14. The method of claim 9, wherein during the implantation, an implanted impurity penetrates through the body layer to reach the epitaxy semiconductor layer.

15. The method of claim 9, wherein the first portion, the second portion, and the third portion of the conductive field plate are physically connected to form the integral region.

16. A method comprising:

forming a gate dielectric layer over a body layer, wherein the body layer is over a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space, with an intermediate portion of the gate dielectric layer being in the space;

implanting a portion of the body layer underlying the intermediate portion of the gate dielectric layer to form a doped semiconductor region of the first conductivity type, wherein during the implantation, an implanted impurity is implanted to penetrate through the body layer, so that the doped semiconductor region extends into the semiconductor layer;

forming a conductive field plate comprising;

a first portion overlapping the first gate electrode;

a second portion over the second gate electrode; and

a third portion in the space, wherein the first portion, the second portion, and the third portion are connected to form an integral region;

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode;

etching portions of the body layer to expose sidewalls of the heavily doped regions;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region and the intermediate portion of the gate dielectric layer, wherein the source region is in contact with the sidewalls of the heavily doped regions;

forming an inter-layer dielectric overlapping the integral region, wherein the inter-layer dielectric separates the integral region from a portion of the source region overlapping the integral region; and

forming a drain region underlying the semiconductor layer.

17. The method of claim 16, wherein in the implanting, the first gate electrode and the second gate electrode are used as a portion of an implantation mask.

18. The method of claim 16, wherein the source region is in contact with the sidewalls of the heavily doped regions to form vertical planes substantially perpendicular to an interface between the gate dielectric layer and the body layer.

19. The method of claim 16, wherein the source region comprises a portion filled into the space, with the portion of the source region level with the first gate electrode and the second gate electrode.