Semiconductor device including a gate trench having a gate electrode located above a buried electrode

• US 9,673,318 B1
• Filed: 01/13/2016
• Issued: 06/06/2017
• Est. Priority Date: 01/13/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Mirchandani, Ashita, Henson, Timothy D.
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/995,049
• Time in Patent Office: 510 Days
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a base region situated over a drift region;

a source trench extending through said base region and into said drift region, said source trench having a shield electrode; and

a gate trench extending through said base region and into said drift region, said gate trench having a gate electrode situated above a buried electrode,

wherein said source trench is separated from said gate trench on all sides by said base region,

wherein said source trench and said gate trench are non-intersecting.

2. The semiconductor device of claim 1, wherein said source trench is surrounded by said gate trench.

3. The semiconductor device of claim 1, wherein said shield electrode is coupled to a source contact over said semiconductor substrate.

6. The semiconductor device of claim 1, wherein said gate trench includes gate trench dielectrics lining a bottom and sidewalls of said gate trench.

7. The semiconductor device of claim 1, wherein said source trench includes source trench dielectrics lining a bottom and sidewalls of said source trench.

8. The semiconductor device of claim 1, wherein said shield electrode in said source trench and said buried electrode in said gate trench are coupled to a source potential.

4. The semiconductor device of claim further comprising a source region over said base region.

5. The semiconductor device of claim 4, wherein said source region is electrically coupled to said shield electrode.

9. A semiconductor device, comprising:

a semiconductor substrate having a base region situated over a drift region;

a doped pillar portion of the semiconductor substrate extending into said drift region;

a gate trench extending through said base region and into said drift region;

said gate trench surrounding said doped pillar, said gate trench having a gate electrode situated above a buried electrode.

10. The semiconductor device of claim 9, wherein said doped pillar is situated below said base region.

11. The semiconductor device of claim 9, wherein said doped pillar is situated below and coupled to a source contact.

12. The semiconductor device of claim 9, wherein said gate trench includes gate trench dielectrics lining a bottom and sidewalls of said gate trench.

13. The semiconductor device of claim 9, wherein said buried electrode is insulated from said gate electrode in said gate trench.

14. The semiconductor device of claim 9, wherein said doped pillar and said buried electrode are coupled to a source potential.

15. A transistor, comprising:

a semiconductor substrate having a drift region situated over a drain region, and a base region situated over said drift region;

a source trench extending through said base region and into said drift region, said source trench having a shield electrode; and

a gate trench extending through said base region and into said drift region, said gate trench having a gate electrode situated above a buried electrode,

wherein said source trench is separated from said gate trench on all sides by said base region,

wherein said source trench and said gate trench are non-intersecting.

16. The transistor of claim 15, wherein said source trench is surrounded by said gate trench.

17. The transistor of claim 15, further comprising source regions situated over said base region and electrically coupled to said shield electrode.

18. The transistor of claim 15, wherein said source trench includes source trench dielectrics on a bottom and sidewalls of said source trench.

19. The transistor of claim 15, wherein said gate trench includes gate trench dielectrics on a bottom and sidewalls of said gate trench.

20. The transistor of claim 15, wherein said shield electrode in said source trench and said buried electrode in said gate trench are coupled to a source potential.