Methods of forming memory arrays

• US 9,673,393 B2
• Filed: 05/03/2016
• Issued: 06/06/2017
• Est. Priority Date: 06/04/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pellizzer, Fabio
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US15/145,654
• Publication Number:
  US 20160248010A1
• Time in Patent Office: 399 Days
• Field of Search: 438128, 257208, 257E23141, 257E21645
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/061 Shaping switching materials
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

Claims

1. A method of forming a memory array, comprising:

forming first access/sense material over a semiconductor substrate;

patterning the first access/sense material into first lines extending along a first direction;

the first lines comprising a first series of access/sense lines;

forming programmable material over the first lines;

patterning the programmable material into diagonal lines that cross the first lines;

the diagonal lines extending along a diagonal direction that is not parallel to the first direction and that is not orthogonal to the first direction;

forming second access/sense material over the diagonal lines;

patterning the second access/sense material into second lines extending along a second direction;

the second direction being substantially orthogonal to the first direction;

the second lines comprising a second series of access/sense lines; and

transferring a pattern from the second lines into the programmable material to singulate the programmable material into individual memory cells;

the programmable material within the memory cells having sidewalls which extend diagonally relative to sidewalls of the access/sense lines of the first and second series;

each of the memory cells being uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series.

2. The method of claim 1 wherein the diagonal direction is about 45°

offset from the first and second directions.

3. The method of claim 1 comprising:

forming a stack comprising select device material over the first access/sense material;

patterning the stack into the first lines extending along the first direction; and

transferring the pattern from the diagonal lines into the select device material to singulate the select device material into a plurality of select devices.

4. The method of claim 3 wherein the stack comprises a first carbon-containing electrode material below the select device material and a second carbon-containing electrode material above the select device material;

and wherein the pattern from the diagonal lines is transferred through the first and second carbon-containing electrode materials to singulate the first and second carbon-containing electrode materials into first and second carbon-containing electrodes, respectively, below and above the select devices.

5. The method of claim 4 wherein the programmable material is formed directly against the second carbon-containing electrode material.

6. The method of claim 4 wherein:

one or more insulative materials are formed over and between the first lines;

planarization is utilized to remove the insulative materials from over the first lines and expose a surface of the second-carbon-containing material; and

the programmable material is formed directly against the exposed surface.

7. The method of claim 6 wherein third carbon-containing electrode material is formed over the programmable material and is patterned with the programmable material by transferring a pattern from the second lines through the third carbon-containing electrode material;

the patterning of the third carbon-containing electrode material singulating the third carbon-containing electrode material into third carbon-containing electrodes.

8. The method of claim 7 wherein the second access/sense material is formed directly against the third carbon-containing electrode material.

9. The method of claim 1 wherein the programmable material comprises phase change material.

10. The method of claim 1 wherein the programmable material comprises chalcogenide.

11. The method of claim 1 wherein the programmable material comprises germanium, antimony and tellurium.

12. A method of forming a memory array, comprising:

forming a stack over a semiconductor substrate;

the stack comprising a first region of programmable material over a first access/sense material;

patterning the stack into first lines extending along a first direction;

the first lines comprising a first series of access/sense lines;

forming a second region of programmable material over the first lines;

patterning the second region of programmable material into diagonal lines that cross the first lines;

the diagonal lines extending along a diagonal direction that is not parallel to the first direction and that is not orthogonal to the first direction;

transferring a pattern from the diagonal lines into the first region of the programmable material to singulate the first region of the programmable material into first programmable material portions of memory cells;

the first programmable material portions being configured as first polygonal structures having a first peripheral shape;

forming second access/sense material over the diagonal lines;

patterning the second access/sense material into second lines extending along a second direction;

the second direction being substantially orthogonal to the first direction;

the second lines comprising a second series of access/sense lines;

transferring a pattern from the second lines into the second region of the programmable material to singulate the second region of the programmable material into second programmable material portions of the memory cells;

the second programmable material portions being configured as second polygonal structures having a second peripheral shape different from the first peripheral shape; and

wherein each of the memory cells is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series.

13. The method of claim 12 wherein the first and second regions of programmable material are a same composition as one another.

14. The method of claim 13 wherein:

the stack comprises separating material over the first region of programmable material;

the second region of programmable material is formed over the separating material; and

the memory cells comprise the second programmable material portions spaced from the first programmable material portions by the separating material.

15. The method of claim 14 wherein the separating material comprises carbon.

16. The method of claim 12 wherein the first and second regions of programmable material are different compositions relative to one another.

17. The method of claim 12 wherein the stack comprises select device material between the first access/sense material and the first region of programmable material;

and wherein the pattern from the diagonal lines is transferred into the select device material to singulate the select device material into a plurality of select devices.

18. A method of forming a memory array, comprising:

forming first access/sense material over a semiconductor substrate;

patterning the first access/sense material into first lines extending laterally relative to an upper surface of the substrate along a first direction;

the first lines comprising a first series of access/sense lines;

forming programmable material over the first lines;

patterning the programmable material into diagonal lines that cross the first lines;

the diagonal lines extending along a diagonal direction that is not parallel to the first direction and that is not orthogonal to the first direction;

forming second access/sense material over the diagonal lines;

patterning the second access/sense material into second lines extending along a second direction;

the second direction being substantially orthogonal to the first direction;

the second lines comprising a second series of access/sense lines; and

singulating the programmable material into individual memory cells that extend vertically upward relative to the upper surface of the substrate;

the programmable material within the memory cells having sidewalls which extend diagonally relative to sidewalls of the access/sense lines of the first and second series.

19. The method of claim 18 wherein the programmable material is a phase change material.

20. The method of claim 18 wherein each of the memory cells is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series.