Multi-lane N-factorial (N!) and other multi-wire communication systems

• US 9,673,961 B2
• Filed: 11/12/2015
• Issued: 06/06/2017
• Est. Priority Date: 04/10/2014
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro
• Primary Examiner(s): Vo, Don N
• Application Number:
  US14/939,692
• Publication Number:
  US 20160065357A1
• Time in Patent Office: 572 Days
• Field of Search: 375355
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Claims

1. An apparatus comprising:

means for receiving a first sequence of symbols from a first lane of a multi-lane interface, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the first lane;

means for recovering a clock signal from the multi-lane interface, wherein the means for recovering the clock signal includes a circuit configured to generate edges in the clock signal corresponding to transitions in the signaling state of the N wires between pairs of consecutive symbols in the first sequence of symbols;

means for converting the first sequence of symbols to a first set of data bits using the clock signal, including a transcoder adapted to convert the first sequence of symbols to a set of transition numbers and to convert the set of transition numbers to the first set of data bits; and

means for deriving a second set of data bits from one or more signals received from a second lane of the multi-lane interface using the clock signal.

2. The apparatus of claim 1, wherein the means for deriving the second set of data bits is configured to operate without transcoding.

3. The apparatus of claim 1, wherein the first sequence of symbols is received in _NC₂ differential signals transmitted on _NC₂ different pairs of the N wires.

4. The apparatus of claim 3, wherein the second lane comprises M wires and a second sequence of symbols is received from _MC₂ differential signals transmitted on _MC₂ different pairs of the M wires, and wherein M is not equal to N.

5. The apparatus of claim 3, wherein the second lane comprises M wires and a second sequence of symbols is received from _MC₂ differential signals transmitted on _MC₂ different pairs of the M wires, and wherein M is equal to N.

6. The apparatus of claim 3, wherein the means for deriving the second set of data bits is configured to:

receive serial signals from each of M wires of a serial interface; and

extract the second set of data bits by sampling the serial signals in accordance with the clock signal.

7. The apparatus of claim 3, wherein the means for deriving the second set of data bits is configured to:

receive M/2 differential signals from M wires of a serial interface; and

extract the second set of data bits by sampling the M/2 differential signals in accordance with the clock signal.

8. The apparatus of claim 1, wherein the second lane comprises M single-ended. wires.

9. The apparatus of claim 1, wherein the clock signal includes one or more edges corresponding to one or more transitions in the signaling state of at least one wire of the second lane of the multi-lane interface.

10. The apparatus of claim 1, wherein the means for recovering the clock signal is configured to:

provide a transition in the clock signal corresponding to a transition detected in the signaling state of the N wires or in the signaling state of one or more wires of the second lane.

11. The apparatus of claim 1, wherein the first sequence of symbols is received from _NC₂ differential signals, each of the _NC₂ differential signals being received from a different pair of the N wires, and a second sequence of symbols is received from _MC₂ differential signals, each of the _MC₂ differential signals being received from a different pair of M wires of the second lane, and wherein the transcoder is further adapted to convert the second sequence of symbols to the second set of data bits.

12. The apparatus of claim 11, wherein a transition in the signaling state of one or more of the N wires and the M wires occurs between each sequential pair of symbols in the first sequence of symbols.

13. A non-transitory processor-readable storage medium, comprising code for:

receiving a first sequence of symbols from a first lane of a multi-lane interface, wherein each symbol in the sequence of symbols corresponds to a signaling state of a plurality of wires of the first lane; and

causing a clock and data recovery (CDR) circuit to recover a clock signal from the multi-lane interface, wherein the clock signal includes edges corresponding to a plurality of transitions in the signaling state of the plurality of wires of the first lane between pairs of consecutive symbols in the first sequence of symbols;

converting the first sequence of symbols to a set of transition numbers using the clock signal;

converting the set of transition numbers to obtain a first set of data bits; and

deriving a second set of data bits from one or more signals received from a second lane of the multi-lane interface using the clock signal.

14. The storage medium of claim 13, wherein the CDR circuit is configured to recover the clock signal by generating an edge in the clock signal based on a determination of a transition in the signaling state of at least one wire of the second lane of the multi-lane interface.

15. The storage medium of claim 13, wherein the second set of data bits is decoded without generating transition numbers.

16. A transmitter comprising:

a first encoding circuit configured to convert first data bits in a set of transition numbers;

a second encoding circuit configured to convert the set of transition numbers to a first sequence of symbols, and to embed clock information in the first sequence of symbols, wherein each symbol in the first sequence of symbols corresponds to a signaling state of N wires of a first lane of a multi-lane interface;

a first plurality of line drivers adapted to transmit the first sequence of symbols on the first lane; and

a second plurality of line drivers adapted to transmit a second sequence of symbols on a second lane of the multi-lane interface, wherein second data hits are encoded in the second sequence of symbols without embedded clock information.

17. The transmitter of claim 16, wherein the second data bits are encoded in the second sequence of symbols without conversion to transition numbers.

18. The transmitter of claim 16, wherein the first plurality of line drivers is configured to transmit the first sequence of symbols in _NC₂ differential signals on _NC₂ different pairs of the N wires.

19. The transmitter of claim 18, wherein the second lane comprises M wires, and wherein the second plurality of line drivers is configured to transmit the second sequence of symbols in _MC₂ differential signals on _MC₂ different pairs of the M wires, wherein M is not equal to N.

20. The transmitter of claim 18, wherein the second sequence of symbols is transmitted on M wires of a serial bus.

21. The transmitter of claim 20, wherein the second plurality of line drivers is configured to transmit the second data bits in M/2 differential signals.

22. The transmitter of claim 16, wherein the second plurality of line drivers comprises single-ended drivers.

23. The transmitter of claim 16, wherein the clock information relates to a transmit clock used to encode both the first sequence of symbols and the second sequence of symbols.

24. The transmitter of claim 16, wherein the second encoding circuit is configured to embed the clock information by causing a transition in the signaling state of the N wires of the first lane or in the signaling state of one or more wires of the second lane between each pair of consecutive symbols transmitted on the first lane.

25. The transmitter of claim 16, wherein the second encoding circuit is configured to encode the first data bits in the first sequence of symbols and to encode the second data bits in the second sequence of symbols.

26. The transmitter of claim 25, wherein the second lane comprises M wires, and wherein the second encoding circuit is configured to embed the clock information by causing a transition in the signaling state of the N wires or in the signaling state of the M wires between transmissions of a pair of consecutive symbols in the first sequence of symbols.

27. The transmitter of claim 25, wherein the first encoding circuit and the second encoding circuit are configured to:

divide data received during a first clock interval to obtain the first data bits and the second data bits; and

transmit a first symbol corresponding to the first data bits on the first lane concurrently with a second symbol corresponding to the second data bits on the second lane.

28. A non-transitory processor-readable storage medium, comprising code for:

embedding clock information in a first sequence of symbols that encodes first data bits, wherein each symbol in the first sequence of symbols corresponds to a signaling state of N wires of a first lane of a multi-lane interface;

transmitting the first sequence of symbols on the first lane; and

transmitting a second sequence of symbols on a second lane of the multi-lane interface, wherein second data bits are encoded in the second sequence of symbols without embedded clock information, wherein embedding the clock information includes;

using a transcoder to convert the first data bits to a set of transition numbers; and

converting the set of transition numbers to obtain the first sequence of symbols.

29. The storage medium of claim 28, wherein the clock information relates to a transmit clock used to encode both the first sequence of symbols and the second sequence of symbols.

30. The storage medium of claim 28, wherein each symbol in the first sequence of symbols is transmitted in a different symbol interval, and wherein the code for embedding clock information includes code for causing a transition in the signaling state of the N wires or in the signaling state of one or more wires of the second lane between each pair of consecutive symbols in the first sequence of symbols.