System and method for reducing false preamble detection in a communication receiver
First Claim
1. An apparatus comprising:
- a signal detection circuit that includes a counter circuit configured to determine a count reached between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval;
a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval;
phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and
a pattern matching circuit configured to match a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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Accused Products
Abstract
An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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Citations
20 Claims
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1. An apparatus comprising:
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a signal detection circuit that includes a counter circuit configured to determine a count reached between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit configured to match a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method to detect a data packet comprising:
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determining whether successive detected edge signals are separated from each other by at least a prescribed time interval; producing clock signal pulses in response to a determination that a succession of detected edge signals each is separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching the produced clock signal pulses with the detected edge signals; and matching a sequence of detected edge signals aligned to the produced clock signal pulses to detect the data packet. - View Dependent Claims (19, 20)
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Specification