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System and method for reducing false preamble detection in a communication receiver

  • US 9,673,962 B1
  • Filed: 02/17/2016
  • Issued: 06/06/2017
  • Est. Priority Date: 02/17/2016
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a signal detection circuit that includes a counter circuit configured to determine a count reached between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval;

    a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval;

    phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and

    a pattern matching circuit configured to match a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

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