Multi-wire open-drain link with data symbol transition based clocking

• US 9,673,968 B2
• Filed: 05/17/2016
• Issued: 06/06/2017
• Est. Priority Date: 03/20/2013
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro, Cheung, Joseph, Wiley, George Alan
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): HUGHES, EBONI N
• Application Number:
  US15/156,555
• Publication Number:
  US 20160261400A1
• Time in Patent Office: 385 Days
• CPC Class Codes: H03K 19/00 Logic circuits, i.e. having at least two inputs acting on one output circuits for computer systems using fuzzy logic G06N7/02; Inverting circuits
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/134 with field-effect transistors
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Claims

1. A method for generating a clock signal, comprising:

detecting a transition between symbols received from a multi-wire communication interface;

generating a clock pulse when the transition between symbols affects state of a first signal received from a first wire of the multi-wire communication interface;

using one or more delay circuits to delay the clock pulse by a preconfigured first interval when the transition between symbols causes a rising edge in the first signal;

using the one or more delay circuits to delay the clock pulse by a preconfigured second interval when the transition between symbols causes a falling edge in the first signal; and

aggregating the clock pulse with at least one additional clock pulse generated in response to the transition between symbols.

2. The method of claim 1, wherein the preconfigured first interval or the preconfigured second interval is selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

3. The method of claim 1, wherein the preconfigured first interval or the preconfigured second interval is configured based on a difference between a rise time and a fall time of the first signal, the difference being associated with an open-drain transistor.

4. The method of claim 3, wherein the preconfigured second interval is selected to match a first delay that is associated with the rise time.

5. The method of claim 4, wherein the preconfigured first interval is selected to match a second delay that is associated with the fall time.

6. The method of claim 1, wherein the at least one additional clock pulse comprises a pulse generated when the transition between symbols affects state of a second signal received from a second wire of the multi-wire communication interface.

7. The method of claim 1, further comprising calibrating the preconfigured first interval or the preconfigured second interval.

8. The method of claim 1, further comprising:

providing a rising calibration transition on the communication interface;

generating a first calibration clock pulse responsive to the rising calibration transition;

calibrating the first interval based on a difference in timing between the rising calibration transition and the first calibration clock pulse;

providing a falling calibration transition on the communication interface;

generating a second calibration clock pulse responsive to the falling calibration transition; and

calibrating the second interval based on a difference in timing between the falling calibration transition and the second calibration clock pulse.

9. The method of claim 8, further comprising:

adjusting a programmed delay of a first delay circuit based on the difference in timing between the rising calibration transition and the first calibration clock pulse; and

adjusting a programmed delay of a second delay circuit based on the difference in timing between the falling calibration transition and the second calibration clock pulse.

10. The method of claim 8, further comprising:

using a timer that reflects a desired delay associated with the first calibration clock pulse and the second calibration clock pulse.

11. An apparatus for generating a clock signal, comprising:

means for detecting a transition between symbols received from a multi-wire communication interface;

means for generating a clock pulse when the transition between symbols affects state of a first signal received from a first wire of the multi-wire communication interface;

means for delaying the clock pulse, including one or more delay circuits configured to;

delay the clock pulse by a preconfigured first interval when the transition between symbols causes a rising edge in the first signal; and

delay the clock pulse by a preconfigured second interval when the transition between symbols causes a falling edge in the first signal; and

means for aggregating the clock pulse with at least one additional clock pulse generated in response to the transition between symbols.

12. The apparatus of claim 11, wherein the preconfigured first interval or the preconfigured second interval is selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

13. The apparatus of claim 11, wherein the preconfigured first interval is calibrated based on a difference in timing between the clock pulse and the transition between symbols when the transition between symbols causes a rising edge in the first signal, and wherein the preconfigured second interval is calibrated based on a difference in timing between the clock pulse and the transition between symbols when the transition between symbols causes a falling edge in the first signal.

14. The apparatus of claim 13, wherein the difference in timing between the clock pulse and the transition between symbols includes a rise time associated with an open-drain transistor.

15. The apparatus of claim 13, wherein the difference in timing between the clock pulse and the transition between symbols includes a fall time associated with an open-drain transistor.

16. The apparatus of claim 11, wherein the at least one additional clock pulse comprises a pulse generated when the transition between symbols affects state of a second signal received from a second wire of the multi-wire communication interface.

17. The apparatus of claim 11, further comprising means for calibrating the preconfigured first interval or the preconfigured second interval.

18. The apparatus of claim 17, wherein the means for calibrating the preconfigured first interval or the preconfigured second interval is configured to:

provide a rising calibration transition on the communication interface;

generate a first calibration clock pulse responsive to the rising calibration transition;

calibrate the first interval based on a difference in timing between the rising calibration transition and the first calibration clock pulse;

provide a falling calibration transition on the communication interface;

generate a second calibration clock pulse responsive to the falling calibration transition; and

calibrate the second interval based on a difference in timing between the falling calibration transition and the second calibration clock pulse.

19. The apparatus of claim 18, wherein the means for calibrating the preconfigured first interval or the preconfigured second interval is configured to:

adjust a programmed delay of a first delay circuit based on the difference in timing between the rising calibration transition and the first calibration clock pulse; and

adjust a programmed delay of a second delay circuit based on the difference in timing between the falling calibration transition and the second calibration clock pulse.

20. The apparatus of claim 18, the means for calibrating the preconfigured first interval or the preconfigured second interval includes a timer that reflects a desired delay associated with the first calibration clock pulse and the second calibration clock pulse.

21. An apparatus for generating a clock signal, comprising:

one or more delay circuits; and

a processing system configured to;

detect a transition between symbols received from a multi-wire communication interface;

generate a clock pulse when the transition between symbols affects state of a first signal received from a first wire of the multi-wire communication interface;

use the one or more delay circuits to delay the clock pulse by a preconfigured first interval when the transition between symbols causes a rising edge in the first signal;

use the one or more delay circuits to delay the clock pulse by a preconfigured second interval when the transition between symbols causes a falling edge in the first signal; and

aggregate the clock pulse with at least one additional clock pulse generated in response to the transition between symbols.

22. The apparatus of claim 21, wherein the preconfigured first interval or the preconfigured second interval is selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

23. The apparatus of claim 21, wherein the preconfigured first interval is calibrated based on a difference in timing between the clock pulse and the transition between symbols when the transition between symbols causes a rising edge in the first signal, and wherein the preconfigured second interval is calibrated based on a difference in timing between the clock pulse and the transition between symbols when the transition between symbols causes a falling edge in the first signal.

24. The apparatus of claim 23, wherein the difference in timing between the clock pulse and the transition between symbols includes a rise time associated with an open-drain transistor, and wherein the difference in timing between the clock pulse and the transition between symbols includes a fall time associated with an open-drain transistor.

25. The apparatus of claim 21, wherein the at least one additional clock pulse comprises a pulse generated when the transition between symbols affects state of a second signal received from a second wire of the multi-wire communication interface.

26. The apparatus of claim 21, wherein the processing system is configured to calibrate the preconfigured first interval or the preconfigured second interval.

27. The apparatus of claim 21, wherein the processing system is configured to:

provide a rising calibration transition on the communication interface;

generate a first calibration clock pulse responsive to the rising calibration transition;

provide a falling calibration transition on the communication interface;

generate a second calibration clock pulse responsive to the falling calibration transition;

determine a difference in timing between the first calibration clock pulse and the second calibration clock pulse; and

modify at least one preconfigured interval by an amount calculated to minimize the difference in timing between the first calibration clock pulse and the second calibration clock pulse.

28. The apparatus of claim 27, wherein the processing system is configured to:

adjust a programmed delay of a first delay circuit based on a measured delay associated with the first calibration clock pulse; and

adjust a programmed delay of a second delay circuit based on a measured delay associated with the second calibration clock pulse.

29. The apparatus of claim 27, wherein the processing system is configured to modify the at least one preconfigured interval using a timer that reflects a desired delay associated with the first calibration clock pulse and the second calibration clock pulse.

30. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

detect a transition between symbols received from a multi-wire communication interface;

generate a clock pulse when the transition between symbols affects state of a first signal received from a first wire of the multi-wire communication interface;

use one or more delay circuits to delay the clock pulse by a preconfigured first interval when the transition between symbols causes a rising edge in the first signal;

use the one or more delay circuits to delay the clock pulse by a preconfigured second interval when the transition between symbols causes a falling edge in the first signal; and

aggregate the clock pulse with at least one additional clock pulse generated in response to the transition between symbols.