Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

• US 9,673,969 B2
• Filed: 01/11/2016
• Issued: 06/06/2017
• Est. Priority Date: 03/07/2013
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Chulkyu, Sengoku, Shoichiro, Wiley, George Alan, Cheung, Joseph
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US14/992,450
• Publication Number:
  US 20160127121A1
• Time in Patent Office: 512 Days
• Field of Search: 375316, 375256, 375257, 375259
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method for performing multi-wire signaling decoding is provided. A raw symbol spread over a plurality of n wires is received via a plurality of differential receivers. The raw symbol is converted into a sequential number from a set of sequential numbers. Each sequential number is converted to a transition number. A plurality of transition numbers is converted into a sequence of data bits. A clock signal is then extracted from the reception of raw symbols.

Claims

1. A method for performing multi-wire signaling decoding, comprising:

receiving a raw symbol spread over n wires via a plurality of differential receivers, where n is an integer greater than 1;

converting the raw symbol into a sequential number from a set of sequential numbers;

converting each sequential number to a transition number;

converting m transition numbers into a sequence of data bits, where m is an integer greater than 1; and

extracting a clock signal from the reception of raw symbols which then serves to synchronize raw symbol reception.

2. The method of claim 1, wherein converting each sequential number to a transition number includes

converting a sequential number into a plurality of transition numbers.

3. The method of claim 1, wherein converting the raw symbol into a sequential number from a set of sequential numbers includes

converting a plurality of raw symbols into a sequential number.

4. The method of claim 1, where the n wires is greater than or equal to three (3).

5. The method of claim 1, where the n wires is greater than or equal to four (4).

6. The method of claim 1, wherein the raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the n wires.

7. The method of claim 1, wherein for an n factorial differential signaling across the n drivers, r^m possible different states are represented by the transition numbers, where r is n!-1.

8. The method of claim 1, wherein the transition number is selected from the sequential number and based on an immediately previous sequential number.

9. A decoding circuit for performing multi-wire signaling decoding, comprising:

a plurality of differential receivers to receive a raw symbol spread over n wires, where n is an integer greater than 1;

a raw symbol-to-sequential number converter for converting the raw symbol into a sequential number from a set of sequential numbers;

a sequential number-to-transition number converter for converting each sequential number to a transition number;

a transition number-to-bits converter for converting m transition numbers into a sequence of data bits, where m is an integer greater than 1; and

a clock data recovery circuit for extracting a clock signal from the reception of raw symbols which then serves to synchronize raw symbol reception.

10. The decoding circuit of claim 9, wherein converting each sequential number to a transition number includes converting a sequential number into a plurality of transition numbers.

11. The decoding circuit of claim 9, wherein converting the raw symbol into a sequential number from a set of sequential numbers includes converting a plurality of raw symbols into a sequential number.

12. The decoding circuit of claim 9, where the n wires is greater than or equal to three (3).

13. The decoding circuit of claim 9, where the n wires is greater than or equal to four (4).

14. The decoding circuit of claim 9, wherein the raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the n wires.

15. The decoding circuit of claim 9, wherein for an n factorial differential signaling across the n drivers, r^m possible different states are represented by the transition numbers, where r is n!-1.

16. The decoding circuit of claim 9, wherein the plurality of differential drivers is equal to _nC₂, where _nC₂=n (n-1)/2.

17. The decoding circuit of claim 9, wherein the plurality of differential drivers is equal to n.

18. The decoding circuit of claim 9, wherein the transition number is selected from the sequential number and based on an immediately previous sequential number.

19. A decoding circuit for performing multi-wire signaling decoding, comprising:

means for receiving a raw symbol spread over n wires via a plurality of differential receivers, where n is an integer greater than 1;

means for converting the raw symbol into a sequential number from a set of sequential numbers;

means for converting each sequential number to a transition number; and

means for converting m transition numbers into a sequence of data bits, where m is an integer greater than 1; and

means for extracting a clock signal from the reception of raw symbols which then serves to synchronize raw symbol reception.