Method and apparatus for high speed chip-to-chip communications

• US 9,674,014 B2
• Filed: 10/22/2015
• Issued: 06/06/2017
• Est. Priority Date: 10/22/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Ulrich, Roger
• Primary Examiner(s): Burd, Kevin M
• Application Number:
  US14/920,762
• Publication Number:
  US 20160119118A1
• Time in Patent Office: 593 Days
• Field of Search: None
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.

Claims

1. An apparatus comprising:

a first simple two-input comparator configured to receive first and second input signals, and to responsively generate a first subchannel output;

a second simple two-input comparator configured to receive third and fourth input signals, and to responsively generate a second subchannel output; and

a third multi-input comparator configured to receive the first, second, third, and fourth input signals, and to responsively generate a third subchannel output;

a first data detector connected to the second subchannel output;

a second data detector connected to the third subchannel output;

a configuration circuit configured to disable the third comparator and the second data detector in a first operating mode and to communicate the first subchannel output to a clock input of the first data detector, and to enable the third comparator and communicate a clock signal to clock inputs of the first and second data detectors in a second operating mode.

2. The apparatus of claim 1, wherein the clock signal is the first subchannel output.

3. The apparatus of claim 1, further comprising a clock recovery circuit configured to generate the clock signal from the first, second, and third subchannel outputs.

4. The apparatus of claim 3, wherein at least one of the first, second, and third subchannel outputs transitions, and the clock signal is generated according to the transition.

5. The apparatus of claim 1, wherein the configuration circuit disables the multi-input comparator using a processor, the processor comprising a register initialized indicating operation in the first operating mode.

6. The apparatus of claim 1, wherein the configuration circuit is configured to disconnect the first, second, third and fourth input signals from the multi-input comparator.

7. The apparatus of claim 1, wherein the configuration circuit is configured to disable to the multi-input comparator by powering down the multi-input comparator.

8. The apparatus of claim 1, wherein the first and second input signals correspond to a differential clock signal.

9. The apparatus of claim 1, wherein the third and fourth input signals correspond to a differential data signal.

10. The apparatus of claim 1, further comprising a decoder configured to decode the first, second, and third subchannel outputs into a set of output data bits.

11. A method comprising:

receiving first and second input signals at a first two-input comparator, and responsively generating a first subchannel output;

receiving third and fourth input signals at a second two-input comparator, and responsively generating a second subchannel output; and

receiving the first, second, third, and fourth input signals at a third multi-input comparator, and responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals; and

configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to first and second operating modes;

in the first operating mode, disabling the third comparator and the second data detector and communicating the first subchannel output to a clock input of the first data detector; and

in the second operating mode, enabling the third comparator and communicating a clock signal to clock inputs of the first and second data detectors in a second operating mode.

12. The method of claim 11, wherein the clock signal is the first subchannel output.

13. The method of claim 11, further comprising generating the clock signal from the first, second, and third subchannel outputs using a clock recovery circuit.

14. The method of claim 13, wherein at least one of the first, second, and third subchannel outputs transitions, and the clock signal is generated according to the transition.

15. The method of claim 11, wherein disabling the multi-input comparator comprises using a processor, the processor comprising a register initialized indicating operation in the first operating mode.

16. The method of claim 11, wherein disabling the multi-input comparator comprises disconnecting the first, second, third and fourth input signals from the multi-input comparator.

17. The method of claim 11, wherein disabling the multi-input comparator comprises powering down the multi-input comparator.

18. The method of claim 11, wherein the first and second input signals correspond to a differential clock signal.

19. The method of claim 11, wherein the third and fourth input signals correspond to a differential data signal.

20. The method of claim 11, further comprising decoding the first, second, and third subchannel outputs into a set of output data bits.