Packet switching

• US 9,674,097 B2
• Filed: 12/08/2014
• Issued: 06/06/2017
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: King, Steven R., Memon, Mazhar I.
• Primary Examiner(s): Elliott, IV, Benjamin H
• Application Number:
  US14/563,267
• Publication Number:
  US 20150195206A1
• Time in Patent Office: 911 Days
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 47/2433 Allocation of priorities to traffic types
• CPC Class Codes: H04L 47/2475 for supporting traffic characterised by the type of applications
• CPC Class Codes: H04L 47/2483 involving identification of individual flows
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6255 queue load conditions, e.g. longest queue first
• CPC Class Codes: H04L 47/627 policing
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip

Abstract

In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Claims

1. An apparatus comprising:

at least one integrated circuit chip comprising;

at least one processor to execute switch control instructions; and

switch circuitry to;

determine flow information from a received packet, wherein the flow information comprises at least one of a source media access control (MAC) address or a destination MAC address of the received packet;

access packet processing policy information associated with the flow information;

determine whether to block the packet based on at least a portion of the flow information, at least a portion of the packet processing policy information, and a mask stored in a content addressable memory;

determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information, wherein the at least a portion of the flow information upon which the at least one action is determined comprises at least one of the source MAC address or the destination MAC address of the received packet; and

execute the at least one action.

2. The apparatus of claim 1, wherein the packet processing policy information is to implement flow-based quality of service through, at least in part, the at least one action.

3. The apparatus of claim 1, wherein the packet processing policy information is to implement Ethernet header-based quality of service through, at least in part, the at least one action.

4. The apparatus of claim 1, wherein the at least one action is to comprise selecting a queue from a plurality of queues and placing the packet in the selected queue.

5. The apparatus of claim 1, wherein the flow information is to comprise a source Medium Access Control (MAC) address of the packet.

6. The apparatus of claim 1, wherein the flow information is to comprise a destination MAC address of the packet.

7. The apparatus of claim 1, wherein the flow information is to comprise a source IP address of the packet.

8. The apparatus of claim 1, wherein the flow information is to comprise a destination IP address of the packet.

9. The apparatus of claim 1, wherein the flow information is to comprise a port of the packet.

10. The apparatus of claim 1, wherein the integrated circuit chip is to further comprise a content addressable memory to store at least a portion of the packet processing policy information.

11. The apparatus of claim 1, wherein the switch circuitry is to comprise programmable reconfigurable logic circuitry.

12. The apparatus of claim 1, wherein the packet processing policy information is to comprise a bit mask to be applied against at least a portion of the packet to determine whether at least one action specified by the packet processing policy information is to be executed in association with the packet.

13. The apparatus of claim 1, wherein the switching circuitry is to change the packet processing policy information in response to an instruction.

14. The apparatus of claim 1, wherein the at least one integrated circuit chip is a single integrated circuit chip.

15. The apparatus of claim 1, wherein the at least one processor is further to generate packet processing policy information.

16. At least one non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the switch circuitry to:

determine flow information from a received packet, wherein the flow information comprises at least one of a source MAC address or a destination MAC address of the received packet;

access packet processing policy information associated with the flow information;

determine whether to block the packet based on at least a portion of the flow information, at least a portion of the packet processing policy information, and a mask stored in a content addressable memory;

determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information, wherein the at least a portion of the flow information upon which the at least one action is determined comprises at least one of the source MAC address or the destination MAC address of the received packet; and

execute the at least one additional action.

17. The medium of claim 16, wherein the packet processing policy information is to implement flow-based quality of service through, at least in part, the at least one action.

18. The medium of claim 16, wherein the packet processing policy information is to implement Ethernet header-based quality of service through, at least in part, the at least one action.

19. The medium of claim 16, wherein the at least one action is to comprise selecting a queue from a plurality of queues and placing the packet in the selected queue.

20. The medium of claim 16, wherein the flow information is to comprise a source Medium Access Control (MAC) address of the packet.

21. The medium of claim 16, wherein the flow information is to comprise a destination MAC address of the packet.

22. The medium of claim 16, wherein the flow information is to comprise a source IP address of the packet.

23. The medium of claim 16, wherein the flow information is to comprise a destination IP address of the packet.

24. The medium of claim 16, wherein the flow information is to comprise a port of the packet.

25. The medium of claim 16, wherein at least a portion of the packet processing policy information is stored in a content addressable memory.

26. The medium of claim 16, wherein the switch circuitry is to comprise programmable reconfigurable logic circuitry.

27. The medium of claim 16, wherein the packet processing policy information is to comprise a bit mask to be applied against at least a portion of the packet to determine whether at least one action specified by the packet processing policy information is to be executed in association with the packet.

28. The medium of claim 16, wherein the switching circuitry is to change the packet processing policy information in response to an instruction.

29. A system comprising:

at least one host processor, a host processor comprising at least one processor core;

machine-readable memory communicatively coupled to the at least one host processor; and

at least one integrated circuit chip comprising;

at least one processor to execute switch control instructions; and

switch circuitry to;

determine flow information from a received packet, wherein the flow information comprises at least one of a source MAC address or a destination MAC address of the received packet;

access packet processing policy information associated with the flow information;

determine whether to block the packet based on at least a portion of the flow information, at least a portion of the packet processing policy information, and a mask stored in a content addressable memory;

determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information, wherein the at least a portion of the flow information upon which the at least one action is determined comprises at least one of the source MAC address or the destination MAC address of the received packet; and

execute the at least one action.

30. The system of claim 29, further comprising at least one network interface controller to receive the received packet.