Integrated MEMS device

• US 9,676,609 B2
• Filed: 05/03/2016
• Issued: 06/13/2017
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Original Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Inventors: Hsieh, Jerwei
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US15/144,896
• Publication Number:
  US 20160244323A1
• Time in Patent Office: 406 Days
• CPC Class Codes: B81B 2201/032 Bimorph and unimorph actuators, e.g. piezo and thermo
• CPC Class Codes: B81B 7/0038 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: B81B 7/0058 for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00817 Avoid thermal destruction
• CPC Class Codes: B81C 1/00825 Protect against mechanical threats, e.g. against shocks, or residues B81C1/00261 take precedence
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: B81C 2201/056 Releasing structures at the end of the manufacturing process
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates

Abstract

An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

Claims

1. An integrated MEMS device, comprising:

a circuit chip, having a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials; and

a device chip, having a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip;

wherein the first structure layer and the second structure layer have different patterns.

2. The device of claim 1, further comprising a second bonding layer between the first structural layer and the first bonding layer, the second bonding layer is composed of a bondable conductive material/materials, and the second bonding layer is bonded to the first bonding layer.

3. The device of claim 2, further comprising a second sacrificial layer between the second bonding layer and the device chip, the second sacrificial layer is composed of a conductive material/materials.

4. The device of claim 1, wherein the first structural layer is a flexible structure.

5. The device of claim 1, wherein the first structural layer is mainly composed of polysilicon, monocrystalline silicon, or amorphous silicon, and the second structural layer is mainly composed of monocrystalline silicon.

6. The device of claim 1, wherein a plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

7. The device of claim 6, wherein the hermetic spaces are in vacuum state.

8. The device of claim 1, wherein the second structural layer has planar surface topography with reflective metal layer deposited on top.

9. The device of claim 1, wherein a cover is disposed above the second structural layer to form a plurality of hermetic spaces enclosed by the cover, the first structural layer, the second structural layer, the first bonding layer, and the circuit chip.

10. An integrated MEMS device, comprising:

a circuit chip, having a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials; and

a device chip, having a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip;

a second bonding layer, between the first structural layer and the first bonding layer, the second bonding layer is composed of a bondable conductive material/materials, and the second bonding layer is bonded to the first bonding layer,

a second sacrificial layer, between the second bonding layer and the device chip, the second sacrificial layer is composed of a conductive material/materials.

11. The device of claim 10, wherein the first structural layer is a flexible structure.

12. The device of claim 10, wherein the first structural layer is mainly composed of polysilicon, monocrystalline silicon, or amorphous silicon, and the second structural layer is mainly composed of monocrystalline silicon.

13. The device of claim 10, wherein a plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

14. The device of claim 10, wherein a piezoresistive sensing unit is formed at least in one of the first structural layer and the second structural layer.

15. An integrated MEMS device, comprising:

a circuit chip, having a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials; and

a device chip, having a second structural layer being connected to the first bonding layer of the circuit chip;

wherein the second structural layer has planar surface topography with reflective metal layer deposited on top.

16. The device of claim 15, further comprising a second bonding layer between the second structural layer and the first bonding layer, the second bonding layer is composed of a bondable conductive material/materials, and the second bonding layer is bonded to the first bonding layer.

17. The device of claim 16, further comprising a second sacrificial layer between the second bonding layer and the device chip, the second sacrificial layer is composed of a conductive material/materials.

18. The device of claim 15, wherein the second structural layer is mainly composed of monocrystalline silicon.

19. The device of claim 15, wherein a plurality of hermetic spaces are enclosed by the second structural layer, the first bonding layer and the circuit chip.

20. The device of claim 15, wherein a piezoresistive sensing unit is formed in the second structural layer.