Two-step interconnect testing of semiconductor dies

• US 9,678,142 B2
• Filed: 04/07/2014
• Issued: 06/13/2017
• Est. Priority Date: 04/08/2013
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Ryckaert, Julien, Marinissen, Erik Jan, Linten, Dimitri
• Primary Examiner(s): Astacio-Oquendo, Giovanni
• Application Number:
  US14/247,019
• Publication Number:
  US 20140300379A1
• Time in Patent Office: 1,163 Days
• Field of Search: 32475403, 324500, 324537, 32475401
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

Claims

1. A method of testing an interconnect in a semiconductor die, comprising:

providing the semiconductor die, wherein the semiconductor die comprises;

a first interconnect-under-test arranged between a first electrical contact element and a second electrical contact element, and

a second interconnect-under-test arranged between a third electrical contact element and a fourth electrical contact element,

wherein the second interconnect-under-test is connected to the first interconnect-under test via an electrical component;

testing a first signal path in the semiconductor die for manufacturing defects, the first signal path comprising a first part of the first interconnect-under-test and a first deviation path from the first interconnect-under-test through the electrical component to the third electrical contact element, thus obtaining first test results, wherein testing the first signal path comprises probing the first electrical contact element and the third electrical contact element;

testing a second signal path in the semiconductor die for manufacturing defects, the second signal path comprising a second part of the first interconnect-under-test and a second deviation path from the first interconnect-under-test through the electrical component to the fourth electrical contact element, thus obtaining second test results, wherein testing the second signal path comprises probing the second electrical contact element and the fourth electrical contact element;

determining whether or not the first interconnect-under-test suffers from manufacturing defects from the first and second test results; and

determining whether or not the second interconnect-under-test suffers from manufacturing defects from the first and second test results,

wherein the first electrical contact element and the third electrical contact element are formed at a first major surface on the same side of the semiconductor die.

2. The method of claim 1,

wherein the first interconnect-under-test comprises a first vertical interconnection between the first electrical contact element and the second electrical contact element formed at a second major surface of the semiconductor die on an opposite side of the first major surface, and

wherein the second interconnect-under-test comprises a second vertical interconnection between the third electrical contact element and the fourth electrical contact element formed at the second major surface of the semiconductor die.

3. The method of claim 2, wherein testing the second signal path further comprises testing a path between the second electrical contact element and the third electrical contact element.

4. The method of claim 1,

wherein the first interconnect-under-test comprises a first horizontal interconnection between the first and second electrical contact elements formed at the first major surface of the semiconductor die, and

wherein the second interconnect-under-test comprises a second horizontal interconnection between the third and fourth electrical contact elements formed at the first major surface of the semiconductor die.

5. The method of claim 4, wherein testing the second signal path comprises testing a path between the second and third electrical contact elements.

6. The method of claim 1, wherein testing the first signal path includes measuring a characteristic of the electrical component.

7. The method of claim 1, wherein the semiconductor die is an active-lite interposer comprising passive and active device components.

8. The method of claim 7, wherein the active-lite interposer is provided, prior to thinning and stacking, with a plurality of vertical interconnects that are buried in a wafer, wherein probing on the first electrical contact element and on the third electrical contact element is performed at a wafer front end, wherein, during probing on the first electrical contact element and on the third electrical contact element, an electrical characterization is performed on the electrical element to determine that a vertical path from the first electrical contact element to the electrical element and from the third electrical contact element to the electrical element exists.

9. The method of claim 8, wherein, after probing on the first electrical contact element and on the third electrical contact element, through-silicon vias (TSVs) of the active-lite interposer are exposed, by thinning the active-interposer, and provided with the second and fourth electrical contact elements, wherein, during probing on the second electrical contact element and on the fourth electrical contact element, an electrical characterization is performed on the electrical element to determine that a vertical path from the second electrical contact element to the electrical element and from the fourth electrical contact element to the electrical element exists.

10. The method of claim 9, further comprising mounting the thinned interposer temporarily on a temporary carrier.

11. A semiconductor die adapted to be tested for manufacturing defects, the semiconductor die comprising:

a surface having a plurality of electrical contact elements;

a first interconnect-under-test between a first electrical contact element and a second electrical contact element;

a second interconnect-under-test between a third electrical contact element and a fourth electrical contact element,

wherein the second interconnect-under-test is connected to the first interconnect-under test via an electrical component;

a first signal path in the semiconductor die configured for testing for manufacturing defects by obtaining first test results, the first signal path comprising a first part of the first interconnect-under-test and a first deviation path from the first interconnect-under-test through the electrical component to the third electrical contact element, wherein the first signal path is configured to be tested by probing the first electrical contact element and the third electrical contact element;

second signal path in the semiconductor die configured for testing for manufacturing defects by obtaining second test results, the second signal path comprising a second part of the first interconnect-under-test and a second deviation path from the first interconnect-under-test through the electrical component to the fourth electrical contact element, wherein the second signal path is configured to be tested by probing the second electrical contact element and the fourth electrical contact element;

wherein at least three of the first electrical contact element, the second electrical contact element, the third electrical contact element and the fourth electrical contact element are formed at a first major surface on the same side of the semiconductor die.

12. The semiconductor die of claim 11,

wherein the first interconnect-under-test comprises a first horizontal interconnection between the first and second electrical contact elements formed at the first major surface of the semiconductor die.

13. The semiconductor die of claim 12, wherein the second interconnect-under-test comprises a second horizontal interconnection between the third a electrical contact element and the fourth electrical element each formed at the first major surface of the semiconductor die.

14. The semiconductor die of claim 11, wherein the first interconnect-under-test comprises a vertical interconnection between the first electrical contact element at the first major surface of the semiconductor die and a second electrical contact element at a second major surface of the semiconductor die opposite to the first major surface.

15. The semiconductor die of claim 14, wherein the third electrical contact element to which the first and second deviation paths connect comprise different contact elements.

16. The semiconductor die of claim 14, wherein the third electrical contact elements to which the first and second deviation paths connect comprise a same contact element.

17. The semiconductor die of claim 11, wherein the electrical component comprises a diode.

18. The semiconductor die of claim 11, wherein the die comprises at least one of a passive interposer, an active-lite interposer or an active interposer.