Dynamic clock and voltage scaling with low-latency switching
First Claim
1. An integrated circuit, comprising:
- a processor module configured to execute software instructions;
a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on control inputs; and
a resource power manager module configured to receive a mode selection from the processor module, the mode selection indicating one of a plurality of operating modes comprising various frequency and voltage modes, the resource power manager module further configured to select one of a plurality of mode registers based on the mode selection, each one of the plurality of mode registers comprising both;
(1) control inputs for operating the plurality of clock divider modules according to a respective one of the plurality of operating modes and to concurrently supply the control inputs from the selected one of the plurality of mode registers to control registers in at least two of the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes; and
(2) associated control inputs to signal a particular voltage level associated with the respective one of the plurality of operating modes, wherein each one of the plurality of mode registers comprises a clock divider value, a clock source selection value, and a clock output enable value, wherein the controller stabilizes the system clock and the silicon oscillator.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.
15 Citations
24 Claims
-
1. An integrated circuit, comprising:
-
a processor module configured to execute software instructions; a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on control inputs; and a resource power manager module configured to receive a mode selection from the processor module, the mode selection indicating one of a plurality of operating modes comprising various frequency and voltage modes, the resource power manager module further configured to select one of a plurality of mode registers based on the mode selection, each one of the plurality of mode registers comprising both;
(1) control inputs for operating the plurality of clock divider modules according to a respective one of the plurality of operating modes and to concurrently supply the control inputs from the selected one of the plurality of mode registers to control registers in at least two of the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes; and
(2) associated control inputs to signal a particular voltage level associated with the respective one of the plurality of operating modes, wherein each one of the plurality of mode registers comprises a clock divider value, a clock source selection value, and a clock output enable value, wherein the controller stabilizes the system clock and the silicon oscillator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 23, 24)
-
-
9. A method for switching operating modes in an integrated circuit, the method comprising:
-
selecting one of a plurality of frequency-voltage modes as a new operating mode for the integrated circuit, each of the frequency-voltage modes specifying clock module controls and voltages for the integrated circuit; signaling the voltages specified by the selected frequency-voltage mode to a power management integrated circuit; selecting one of a plurality of mode registers based on the selected frequency-voltage mode, each one of the plurality of mode registers comprising the clock mode module controls specified by a respective one of the plurality of frequency-voltage modes; and supplying the clock module controls from the selected one of the mode registers to a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on the clock module controls; wherein the clock module controls from the selected one of the mode registers are supplied to control registers in at least two of the plurality of clock divider modules concurrently and wherein each one of the plurality of mode registers further comprises a clock divider value, a clock source selection value, and a clock output enable value. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. An integrated circuit, comprising:
-
a processor module configured to execute software instructions; a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on control inputs; and a means for managing resource power configured to receive a mode selection from the processor module, the mode selection indicating one of a plurality of operating modes comprising various frequency and voltage modes, and configured to select one of a plurality of mode registers based on the mode selection, each one of the plurality of mode registers comprising both;
(1) control inputs for operating the plurality of clock divider modules according to a respective one of the plurality of operating modes, and to concurrently supply the control inputs from the selected one of the mode registers to control registers in at least two of the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes; and
(2) associated control inputs to signal a particular voltage level associated with the respective one of the plurality of operating modes, wherein each one of the plurality of mode registers further comprises a clock divider value, a clock source selection value, and a clock output enable value. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
-
Specification