Addressing for inter-thread push communication

• US 9,678,812 B2
• Filed: 12/22/2014
• Issued: 06/13/2017
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Swanberg, Randal C., Arimilli, Lakshminarayana B., Irish, John D., Starke, William J.
• Primary Examiner(s): Truong, Lechi
• Application Number:
  US14/579,681
• Publication Number:
  US 20160179590A1
• Time in Patent Office: 904 Days
• Field of Search: 719314
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/54 Interprogram communication
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.

Claims

1. A switch of a data processing system, the switch comprising:

integrated circuitry, including;

data buffers for buffering messages;

receive data structure including a plurality of receive entries each uniquely corresponding to a receive window, wherein each of the plurality of receive entries includes addressing information for one or more mailboxes into which messages can be injected via inter-thread push communication;

a send data structure including a plurality of send entries each uniquely corresponding to a send window, wherein each of the plurality of send entries includes a receive window field that identifies one or more receive windows; and

switch logic that, responsive to a request to push a message referenced by an instruction of a sending thread to one or more receiving threads, accesses a send entry among the plurality of send entries selected based on a send window of the sending thread, accesses one or more of the plurality of receive entries selected based on contents of the receive window field accessed in the send entry, and pushes the message to one or more mailboxes of the one or more receiving threads utilizing the addressing information of accessed in the one or more receive entries;

wherein;

each of the plurality of send entries further includes an independently configurable addressing mode field; and

the switch logic employs one of a plurality of different addressing modes based on a configuration of the addressing mode field of the send entry.

2. The switch of claim 1, wherein the plurality of different addressing modes includes an addressing mode supporting 1-to-1 inter-thread push communication between a given pair of send and receive windows.

3. The switch of claim 1, wherein the plurality of different addressing modes includes an addressing mode supporting inter-thread push communication between of multiple sending threads and any of multiple receiving threads through a given pair of send and receive windows.

4. The switch of claim 1, wherein the switch employs a fixed length address for all of the plurality of different addressing modes.

5. The switch of claim 1, wherein:

the send entry further includes a routing information field containing routing information that specifies a route to another data processing system in which a particular mailbox among the one or more mailboxes resides; and

the switch logic pushes the message to the particular mailbox utilizing the routing information.

6. The switch of claim 1, comprising a single integrated circuit chip including the data buffers, the receive data structure, the send data structure, and the switch logic.

7. A data processing system, comprising:

a plurality of processor cores;

one or more memories coupled to the plurality of processor cores;

an interconnect fabric coupled to the plurality of processor cores;

a switch coupled to the interconnect fabric, wherein the switch includes;

data buffers for buffering messages;

a receive data structure including a plurality of receive entries each uniquely corresponding to a receive window, wherein each of the plurality of receive entries includes addressing information for one or more mailboxes into which messages can be injected via inter-thread push communication;

a send data structure including a plurality of send entries each uniquely corresponding to a send window, wherein each of the plurality of send entries includes a receive window field that identifies one or more receive windows; and

switch logic that, responsive to a request to push a message referenced by an instruction of a sending thread to one or more receiving threads, accesses a send entry among the plurality of send entries selected based on a send window of the sending thread, accesses one or more of the plurality of receive entries selected based on contents of the receive window field accessed in the send entry, and pushes the message to one or more mailboxes of the one or more receiving threads utilizing the addressing information accessed in of the one or more receive entries;

wherein;

each of the plurality of send entries further includes an independently configurable addressing mode field; and

the switch logic employs one of a plurality of different addressing modes based on a configuration of the addressing mode field of the send entry.

8. The data processing system of claim 7, wherein the plurality of different addressing modes includes an addressing mode supporting 1-to-1 inter-thread push communication between a given pair of send and-receive windows.

9. The data processing system of claim 7, wherein the plurality of different addressing modes includes an addressing mode supporting inter-thread push communication between of multiple sending threads and any of multiple receiving threads through a given pair of send and receive windows.

10. The data processing system of claim 7, wherein the switch employs a fixed length address for all of the plurality of different addressing modes.

11. The data processing system of claim 7, wherein:

the send entry further includes a routing information field containing routing information that specifies a route to another data processing system in which a particular mailbox among the one or more mailboxes resides; and

the switch logic pushes the message to the particular mailbox utilizing the routing information.

12. The data processing system of claim 7, comprising a single integrated circuit chip including the data buffers, the receive data structure, the send data structure, and the switch logic.