Storage module and method for on-chip copy gather

• US 9,678,832 B2
• Filed: 01/13/2015
• Issued: 06/13/2017
• Est. Priority Date: 09/18/2014
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Manohar, Abhijeet, Tuers, Daniel E., Gorobets, Sergei
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/595,939
• Publication Number:
  US 20160085464A1
• Time in Patent Office: 882 Days
• Field of Search: 714 4, 714764, 714766, 714807, 711165
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 7/1009 Data masking during input/output

Abstract

A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

Claims

1. A method comprising:

performing the following in a memory that comprises a plurality of word lines and a plurality of data latches;

copying a first error correction code (ECC) page from a first word line into a first data latch;

copying a second ECC page from a second word line into a second data latch;

copying both the first ECC page from the first data latch and the second ECC page from the second data latch into a third data latch; and

copying the first ECC page and the second ECC page from the third data latch to a third word line.

2. The method of claim 1 further comprising maintaining column alignment when copying the first ECC page and the second ECC page from the first and second data latches into the third data latch.

3. The method of claim 1, wherein at least one of the first ECC page or the second ECC page stored in the third word line is in a different column than where the one of the first ECC page or the second ECC page was initially stored in the first or second word line.

4. The method of claim 1 further comprising limiting a number of times an on-chip copy gather operation is performed in the memory.

5. The method of claim 1, wherein the copying is performed only if it is determined that an error rate for the memory is below a threshold.

6. The method of claim 1 further comprising sending at least one of the first ECC page from the first word line or the second ECC page from the second word line to a controller of the device for error testing.

7. The method of claim 1 further comprising performing error correction on at least one of the first ECC page from the first word line or the second ECC page from the second word line using historical error locations from a bit mask.

8. The method of claim 1 further comprising storing data from a host in communication with the device in the third word line, along with the first ECC page and the second ECC page from the third data latch.

9. The method of claim 1, wherein the copying is performed in response to a command from a controller in the device, and wherein the command contains the following fields:

source column, source latch name, destination column, destination latch name, and length of copy.

10. The method of claim 1, wherein the memory is a three-dimensional memory.

11. The method of claim 1, wherein the storage module is embedded in a host.

12. The method of claim 1, wherein the device is removably connected to a host.

13. The method of claim 1, wherein the device is a solid-state drive.

14. A device comprising:

a memory comprising a plurality of word lines and a plurality of data latches; and

an on-chip copy gather circuit in communication with the memory, wherein the on-chip copy gather circuit is configured to use the plurality of data latches to gather data from portions of source word lines and copy the gathered data to a destination word line.

15. The device of claim 14, wherein the on-chip copy gather circuit is further configured to prevent accumulation of errors from bad columns in the memory.

16. The device of claim 15, wherein the on-chip copy gather circuit is configured to prevent accumulation of errors from bad columns in the memory by maintaining column alignment of the data when copying the gathered data.

17. The device of claim 15, wherein the on-chip copy gather module is configured to prevent accumulation of errors from bad columns in the memory by limiting a number of times an on-chip copy gather operation is performed in the memory.

18. The device of claim 15, wherein the on-chip copy gather circuit is configured to prevent accumulation of errors from bad columns in the memory by performing an on-chip copy gather operation only if it is determined that an error rate for the memory is below a threshold.

19. The device of claim 15, wherein the on-chip copy gather circuit is configured to prevent accumulation of errors from bad columns in the memory by error testing the data.

20. The device of claim 14, wherein the memory is a three-dimensional memory.

21. The device of claim 14, wherein the device is embedded in a host.

22. The device of claim 14, wherein the device is removably connected to a host.

23. The device of claim 14, wherein the device is a solid-state drive.

24. A device comprising:

a memory comprising a plurality of word lines and a plurality of data latches; and

a controller in communication with the memory, wherein the controller is configured to gather a first error correction code (ECC) codeword from a first source word line of a plurality of source word lines and a second ECC codeword from a second source word line of the plurality of source word lines in the memory and copy the gathered first ECC codeword and the second ECC codeword to a destination word line while preventing accumulation of errors from bad columns in the memory.

25. The device of claim 24, wherein the controller is configured to prevent accumulation of errors from bad columns in the memory by maintaining column alignment of the first ECC codeword and the second ECC codeword when copying the gathered first ECC codeword and the second ECC codeword.

26. The device of claim 24, wherein the controller is configured to prevent accumulation of errors from bad columns in the memory by limiting a number of times an on-chip copy gather operation is performed in the memory.

27. The device of claim 24, wherein the controller is configured to prevent accumulation of errors from bad columns in the memory by performing an on-chip copy gather operation only if it is determined that an error rate for the memory is below a threshold.

28. The device of claim 24, wherein the controller is configured to prevent accumulation of errors from bad columns in the memory by error testing at least one of the first ECC codeword or the second ECC codeword.

29. The device of claim 24, wherein the memory is a three-dimensional memory.

30. The device of claim 24, wherein the device is embedded in a host.

31. The device of claim 24, wherein the device is removably connected to a host.

32. The device of claim 24, wherein the device is a solid-state drive.