Techniques for indicating a preferred virtual processor thread to service an interrupt in a data processing system
First Claim
1. A method of handling interrupts in a data processing system, the method comprising:
- receiving, at an interrupt presentation controller (IPC), an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore;
determining, by the IPC, a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted;
in response to two or more virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determining, by the IPC, whether multiple of the two or more virtual processor threads do not have a pending interrupt; and
in response to determining that multiple of the two or more virtual processor threads do not have a pending interrupt, selecting, by the IPC, one of the two or more virtual processor threads to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more virtual processor threads.
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Abstract
A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.
51 Citations
20 Claims
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1. A method of handling interrupts in a data processing system, the method comprising:
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receiving, at an interrupt presentation controller (IPC), an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore; determining, by the IPC, a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted; in response to two or more virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determining, by the IPC, whether multiple of the two or more virtual processor threads do not have a pending interrupt; and in response to determining that multiple of the two or more virtual processor threads do not have a pending interrupt, selecting, by the IPC, one of the two or more virtual processor threads to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more virtual processor threads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processing unit for a multithreaded data processing system, the processing unit comprising:
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an interrupt source controller (ISC); and an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to; receive an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore; determine a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted; in response to two or more virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether multiple of the two or more virtual processor threads do not have a pending interrupt; and in response to determining that multiple of the two or more virtual processor threads do not have a pending interrupt, select one of the two or more virtual processor threads to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more virtual processor threads. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
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an interrupt source controller (ISC); and an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to; receive an event notification message (ENM), wherein the ENM specifies an event target number and a number of bits to ignore; determine a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted; in response to two or more virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether multiple of the two or more virtual processor threads do not have a pending interrupt; and in response to determining that multiple of the two or more virtual processor threads do not have a pending interrupt, select one of the two or more virtual processor threads to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more virtual processor threads. - View Dependent Claims (18, 19, 20)
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Specification