Positive feedback enhanced switching equalizer with output pole tuning

• US 9,679,509 B2
• Filed: 01/16/2015
• Issued: 06/13/2017
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Display Company Limited (Samsung Group)
• Inventors: Song, Sanquan
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US14/599,421
• Publication Number:
  US 20150319020A1
• Time in Patent Office: 879 Days
• Field of Search: 375229-332
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/03949 equalizer selection or adaptation based on feedback multiple signaling inclusive of a precoding command for adapting the transmitter H04L1/0031; feedback for transmit diversity systems H04B7/0619; selection of codebook or precoding matrix for MIMO diversity systems H04B7/0456
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005

Abstract

A switched equalizer for equalizing the frequency response of a channel with high-frequency attenuation. In one embodiment the differential input of the equalizer is fed to a switch that interchanges the complementary signals at the differential input, changing the sign of the received signal, at each transition of a clock at the Nyquist frequency. The switched signal is filtered by a low-pass filter with positive feedback enhancement at DC gain and digitized by a sense amplifier, and the digital output of the sense amplifier is inverted during every half-cycle of clock at the Nyquist frequency, restoring the sign of the input signal.

Claims

1. A system for equalizing a data transmission channel, the system having an input and an output and comprising:

a first switch connected to the input, the first switch being to preserve or reverse a polarity of a signal transmitted by the first switch, depending on a setting of the first switch;

a low-pass filter electrically connected to the first switch,

the low-pass filter comprising an amplifier with positive feedback;

a clocked comparator connected to the low-pass filter; and

a switched inverter connected to the clocked comparator, the switched inverter having a data input, a data output, and a control input, and the switched inverter being to receive a digital signal and to output the digital signal or the inverse of the digital signal, depending on a signal at the control input.

2. The system of claim 1, wherein the first switch is to operate in either a first state or a second state.

3. The system of claim 2, wherein the first switch is to receive a differential signal carried on a first conductor and a second conductor.

4. The system of claim 3, wherein the first switch is to transmit, to the low-pass filter, a differential signal carried on a third conductor and a fourth conductor.

5. The system of claim 4, wherein, in the first switch,

in the first state:

the first conductor is connected to the third conductor, and

the second conductor is connected to the fourth conductor, and

in the second state;

the first conductor is connected to the fourth conductor, and

the second conductor is connected to the third conductor.

6. The system of claim 1, wherein the switched inverter comprises:

a switched inverter input,

a switched inverter output,

a first inverter connected to the switched inverter input, and

a single-pole double-throw (SPDT) switch connected to;

the switched inverter input,

the output of the first inverter, and

the switched inverter output.

7. The system of claim 6, wherein the SPDT switch comprises a common terminal, a first switched terminal, and a second switched terminal, and

the first switched terminal of the SPDT switch is connected to the switched inverter input,

the second switched terminal of the SPDT switch is connected to an output of the first inverter, and

the common terminal of the SPDT switch is connected to the switched inverter output.

8. The system of claim 7, wherein the SPDT switch comprises a multiplexer comprising a plurality of transistors.

9. The system of claim 8, wherein the SPDT switch comprises two tri-state inverters,

each of the two tri-state inverters comprising a data input, a data output, and a control input,

the outputs of the two tri-state inverters forming the common terminal of the SPDT switch, and

the control inputs of the two tri-state inverters being connected such that a first one of the two tri-state inverters is in a high-impedance state when a second one of the two tri-state inverters is in a low-impedance state.

10. The system of claim 1, wherein the amplifier with positive feedback comprises a differential amplifier comprising a first transistor, a second transistor, a differential input, and a differential output;

each of the first and second transistors comprising;

a first current-carrying terminal,

a control terminal, and

a second current-carrying terminal;

the differential input comprising;

a first conductor connected to the control terminal of the first transistor, and

a second conductor connected to the control terminal of the second transistor; and

the differential output comprising;

a first conductor connected to the first current-carrying terminal of the first transistor, and

a second conductor connected to the first current-carrying terminal of the second transistor.

11. The system of claim 10, wherein the differential amplifier further comprises:

a third transistor and a fourth transistor, each of the third and fourth transistors comprising;

a first current-carrying terminal,

a control terminal, and

a second current-carrying terminal;

the third transistor connected in series between the first current-carrying terminal of the first transistor and a positive voltage supply; and

the fourth transistor connected in series between the first current-carrying terminal of the second transistor and the positive voltage supply.

12. The system of claim 11, wherein the control terminal of the third transistor is connected to the first current-carrying terminal of the second transistor, and the control terminal of the fourth transistor is connected to the first current-carrying terminal of the first transistor.

13. The system of claim 12, further comprising:

a first programmable resistor connected between;

the first current-carrying terminal of the first transistor and

the positive voltage supply;

a second programmable resistor connected between;

the first current-carrying terminal of the second transistor and

the positive voltage supply;

a first programmable capacitor connected between;

the first current-carrying terminal of the first transistor and

a ground connection; and

a second programmable capacitor connected between;

the first current-carrying terminal of the second transistor and

the ground connection.

14. The system of claim 11, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are field-effect transistors (FETs).

15. A display, comprising:

a timing controller;

a driver integrated circuit (IC); and

a serial data link connecting the timing controller and the driver IC,

the driver IC comprising the system of claim 1.

16. The display of claim 15, wherein the display is an organic light emitting diode (OLED) display or a liquid crystal display (LCD).