Electroentropic memory device

• US 9,679,630 B2
• Filed: 11/04/2016
• Issued: 06/13/2017
• Est. Priority Date: 11/06/2015
• Status: Active Grant

• Current Assignee: Carver Scientific Inc.
• Original Assignee: Carver Scientific Inc.
• Inventors: Carver, David Reginald, Hall, Sean Claudius, Andrepont, Chase Koby, Gibbs, Jaime Hayes, Reynolds, Sean William, Fulfer, Bradford Wesley
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/343,779
• Publication Number:
  US 20170133077A1
• Time in Patent Office: 221 Days
• Field of Search: 365108, 365145, 365163, 365222
• CPC Class Codes: C08L 101/12 characterised by physical features, e.g. anisotropy, viscosity or electrical conductivity liquid crystal materials or compositions C09K19/00
• CPC Class Codes: C08L 2203/20 use in electrical or conductive gadgets
• CPC Class Codes: C08L 2205/025 containing two or more polymers of the same hierarchy C08L, and differing only in parameters such as density, comonomer content, molecular weight, structure
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: H01G 7/02 Electrets, i.e. having a permanently-polarised dielectric
• CPC Class Codes: H01G 7/021 having an organic dielectric
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02

Abstract

Embodiments of an electroentropic memory device comprising an array of electroentropic storage devices (EESDs) are disclosed, as well as methods of making and using the electroentropic memory device. The memory device includes a plurality of address lines arranged in rows to select a row of the EESDs and a plurality of data lines arranged in columns to select a column of the EESDs, wherein each EESD is coupled in series between an address line connected to one side of the EESD and a data line connected to an opposing side of the EESD. The memory device may have a stacked architecture with multiple layers of address lines, data lines, and EESDs. The disclosed electroentropic memory devices are operable in ROM and RAM modes. EESDs in the disclosed electroentropic memory devices may include from 2-4096 logic states and/or have a density from 0.001 kb/cm³ to 1024 TB/cm³.

Claims

1. A memory device, comprising:

an array of electroentropic storage devices (EESDs), each EESD comprising a dielectric material having a relative permittivity greater than 3.9, wherein each EESD is a storage element in the memory device;

a plurality of address lines arranged in rows to select a row of the EESDs; and

a plurality of data lines arranged in columns to select a column of the EESDs, wherein each EESD is coupled in series between an address line connected to one side of the EESD and a data line connected to an opposing side of the EESD.

2. The memory device of claim 1, wherein there is a spatial separation at each intersection where a data line crosses an address line, and each of the spatial separations is occupied by an EESD coupled in series between the address line and the data line.

3. The memory device of claim 1, wherein the dielectric material comprises a plurality of polymeric molecules.

4. The memory device of claim 3, wherein the polymeric molecules comprise proteins, poly(p-xylylene), acrylic acid polymers, methacrylic acid polymers, polyethylene glycol, urethane polymers, epoxy polymers, silicone polymers, terpenoid polymers, naturally occurring resin polymers, polyisocyanates, or combinations thereof.

5. The memory device of claim 3, wherein the dielectric material further comprises an inorganic salt.

6. The memory device of claim 5, wherein the dielectric material further comprises a permittivity increasing material including Y, Ni, Sm, Sc, Tb, Yb, La, Te, Ti, Zr, Ge, Mg, Pb, Hf, Cu, Ta, Nb, Bi, or a combination thereof, which is substantially evenly distributed throughout the material.

7. The memory device of claim 1, wherein each of the plurality of address lines and/or the plurality of data lines comprises an electrically insulated metal, a carbonized polymer, conductive carbon, or an electrically conductive polymer.

8. The memory device of claim 1, wherein:

the memory device does not include a transistor;

or

the memory device includes one or more transistors, and the memory device has a transistor to EESD ratio of less than 1.

9. The memory device of claim 1, wherein each EESD has a logic state determined by a voltage applied between the address line and the data line to which the EESD is coupled.

10. The memory device of claim 9, wherein the EESD has an intrinsic capacitance, the applied voltage modifies the intrinsic capacitance;

and the intrinsic capacitance of the EESD remains unchanged when the applied voltage is removed.

11. The memory device of claim 10, wherein:

(i) the EESD has from 2-4096 logic states;

(ii) the EESD has a volume of 0.00001-10000 μ

m³;

(iii) the EESD has a density within a range of from 0.01 kb to 1024 TB per cm³;

or

(iv) any combination of (i), (ii), and (iii).

12. The memory device of claim 1, wherein the plurality of address lines or the plurality of data lines is disposed on a non-silicon substrate.

13. The memory device of claim 1 having a layered structure, the layered structure comprising:

a first layer comprising the plurality of address lines arranged in rows;

a second layer comprising the plurality of data lines arranged in columns, wherein there are first spatial separations at each intersection where data line of the second layer crosses an address line of the first layer;

the array of EESDs, wherein the EESDs of the array are located in the first spatial separations and each EESD is coupled in series between an address line of the first layer connected to one side of the EESD and data line of the second layer connected to an opposing side of the EESD;

a third layer of address lines arranged in rows crossing the second layer of data lines, wherein there are second spatial separations at each intersection where an address line of the third layer crosses a data line of the second layer; and

a second array of EESDs, wherein each EESD of the second array is a storage element in the memory device, and wherein the EESDs of the second array are located in the second spatial separations and each EESD of the second array is coupled in series between electrode data line of the second layer connected to one side of the EESD and an address line of the third layer connected to an opposing side of the EESD.

14. The memory device of claim 13, further comprising:

a fourth layer of data lines arranged in columns crossing the third layer of address lines, wherein there are third spatial separations at each intersection where a data line of the fourth layer crosses an address line of the third layer; and

a third array of EESDs, wherein each EESD of the third array is a storage element in the memory device, and wherein the EESDs of the third array are located in the third spatial separations and each EESD of the third array is coupled in series between an address line of the third layer connected to one side of the EESD and a data line of the fourth layer connected to an opposing side of the EESD.

15. A method of refreshing a memory device, comprising:

providing an array of entropic energy storage devices (EESDs), wherein each EESD is a storage element in the memory device;

charging an EESD in the array to a voltage V1, wherein the voltage V1 discharges, at least in part, due to leakage over time;

subsequently determining a capacitance C of the EESD;

determining, based on the capacitance C, the voltage V1, wherein the capacitance C is correlated to the voltage V1 and the capacitance C remains substantially unchanged as the voltage V1 discharges due to leakage; and

recharging the EESD to the voltage V1.

16. The method of claim 15, wherein the capacitance C is correlated to the voltage V1 and the capacitance C remains substantially unchanged as the voltage V1 discharges due to leakage.

17. The method of claim 15, wherein determining the capacitance C of the EESD comprises:

reading a voltage V of the EESD;

applying a perturbing charge dQ to the EESD, wherein the perturbing charge dQ has a magnitude sufficient to induce a change in the voltage V without inducing a change in the capacitance C;

subsequently reading a voltage V′

of the EESD; and

determining the capacitance C, where C=dQ/(V′

−

V).

18. The method of claim 17, wherein the perturbing charge dQ:

has a magnitude approximately equal to a magnitude of discharge due to leakage over time;

or

has a magnitude within a range of 1×

10<sup>−

15</sup> coulombs to 1×

10<sup>−

2</sup> coulombs.

19. The method of claim 15, wherein determining the initial voltage V1 prior to leakage comprises comparing the capacitance C of the EESD to predetermined capacitance values for the EESD in charged and uncharged states, thereby correlating the capacitance C to the voltage V1.

20. The method of claim 15, wherein recharging the EESD to the voltage V1 comprises:

selecting a voltage V2 sufficient to recharge the EESD to the voltage V1; and

writing the selected voltage V2 to the EESD, thereby recharging the EESD to the voltage V1.