Method and apparatus for reducing read latency for a block erasable non-volatile memory

• US 9,679,658 B2
• Filed: 06/26/2015
• Issued: 06/13/2017
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Ruby, Paul D., Guo, Xin, Dayacap, Justin R., Doller, Joseph F., Frickey, Robert E., Pelster, David J., Wakchaure, Yogesh B.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/752,817
• Publication Number:
  US 20160379715A1
• Time in Patent Office: 718 Days
• Field of Search: 36518511, 36518512, 36518517, 36518518, 36518519, 36518522, 36518529, 36518533
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Claims

1. An apparatus, comprising:

a non-volatile memory; and

memory control logic to;

generate a command to perform a portion of a block erase operation with respect to a block, wherein the block comprises a block of pages in the non-volatile memory;

perform at least one read or write operation with respect to a page after executing the command; and

generate an additional instance of the command to perform an additional portion of the block erase operation with respect to the block in response to determining that the block erase operation of the block did not complete after performing the at least one read or write operation, wherein each of multiple instances of the command are interleaved with read or write operations by generating each of the instances of the command between a plurality of read or write operations until the block erase operation completes, wherein interleaving the instances of the command limits a number of the write operations before executing the command so that the block is successfully erased by a time a block of pages is written.

2. The apparatus of claim 1, wherein the interleaving the instances of the command generates each of the instances of the command after performing a predetermined number of write operations.

3. The apparatus of claim 1, wherein the interleaving the instances of the command continues to perform read operations without generating an instance of the command, wherein only to perform a number of write operations and not read operations causes the instance of the command to be generated.

4. The apparatus of claim 1, wherein the command is executed to perform a pulse and verify operation to apply a pulse of voltage to cells of the block subject to the block erase operation and to verify whether the cells subject to the block erase operation are in an erased state.

5. The apparatus of claim 1, wherein the non-volatile memory is implemented in a plurality of memory devices having memory cells, and wherein the memory control logic is located external to the memory devices in the apparatus including the memory devices and the memory control logic.

6. The apparatus of claim 1, wherein the non-volatile memory is implemented in a plurality of memory devices including memory cells, and wherein the memory control logic comprises a controller external to the memory devices and component logic implemented on each of the memory devices, wherein the component logic on the memory devices having the memory cells executes the instances of the command, wherein to perform the at least one read or write operation and to determine the block erase operation did not complete are performed by the component logic.

7. An apparatus, comprising:

a non-volatile memory implemented in a plurality of memory devices including memory cells; and

a memory control logic comprising a controller external to the memory devices and a component logic implemented on each of the memory devices to;

generate, by the controller, a command, executed by the component logic, to perform a portion of a block erase operation with respect to a block in the non-volatile memory;

communicate, by the controller, a number of instances of the command to perform the block erase operation to the component logic;

perform, by the component logic, the number of the instances of the command in response to the number of the instances of the command communicated by the controller;

perform, by the component logic, at least one read or write operation after executing each of the number of the instances of the command; and

return, by the component logic, a fail for the block erase operation to the controller in response to the block erase operation not completing after performing the number of the instances of the command; and

returning, by the component logic, a pass for the block erase operation to the controller in response to the block erase operation completing after performing the number of the instances of the command.

8. A memory controller coupled to a non-volatile memory, comprising:

a memory control logic that when executed performs operations, the operations comprising;

generate a command to perform a portion of a block erase operation with respect to a block, wherein the block comprises a block of pages in the non-volatile memory;

perform at least one read or write operation with respect to a page after executing the command; and

generate an additional instance of the command to perform an additional portion of the block erase operation with respect to the block in response to determining that the block erase operation of the block did not complete after performing the at least one read or write operation, wherein each of multiple instances of the command are interleaved with read or write operations by generating each of the instances of the command between a plurality of read or write operations until the block erase operation completes, wherein interleaving the instances of the command limits a number of the write operations before executing the command so that the block is successfully erased by a time a block of pages is written.

9. The memory controller of claim 8, wherein to generate the command and to perform the at least one read or write operation comprises interleaving at least one read or write operation with the instances of the command until the block erase operation of the block completes.

10. The memory controller of claim 9, wherein the interleaving the command generates each of the instances of the command between a plurality of read and write operations.

11. The memory controller of claim 8, wherein the command is executed to perform a pulse and verify operation to apply a pulse of voltage to cells in the block subject to the portion of the block erase operation and to verify whether the cells subject to the block erase operation are in an erased state.

12. The memory controller of claim 8, wherein the non-volatile memory is implemented in a plurality of memory devices having memory cells, and wherein the memory control logic is located external to the memory devices in a non-volatile memory device including the memory devices and the memory control logic.

13. The memory controller of claim 8, wherein the non-volatile memory is implemented in a plurality of memory devices including memory cells, and wherein the memory control logic comprises a controller external to the memory devices and component logic implemented on each of the memory devices, wherein the component logic on the memory devices having the memory cells to erase executes the instances of the command, wherein to perform the at least one read or write operation and to determine that the block erase operation did not complete are performed by the component logic.

14. A method for performing a block erase operation with respect to a non-volatile memory, comprising:

generating a command to perform a portion of a block erase operation with respect to a block a block, wherein the block comprises a block of pages in the non-volatile memory;

performing at least one read or write operation with respect to a page after executing the command; and

generating an additional instance of the command to perform an additional portion of the block erase operation with respect to the block in response to determining that the block erase operation of the block did not complete after performing the at least one read or write operation, wherein each of multiple instances of the command are interleaved with read or write operations by generating each of the instances of the command between a plurality of read or write operations until the block erase operation completes, wherein interleaving the instances of the command limits a number of the write operations before executing the command so that the block is successfully erased by a time a block of pages is written.

15. The method of claim 14, wherein the command is executed to perform a pulse and verify operation to apply a pulse of voltage to cells subject to the portion of the block erase operation and to verify whether the cells subject to the block erase operation are in an erased state.

16. The method of claim 14, wherein the non-volatile memory is implemented in a plurality of memory devices having memory cells, and wherein the operations of generating the instances of the command, determining whether the block erase operation completed, and executing the additional instance of the command are performed by memory control logic located external to the memory devices in a non-volatile memory device including the memory devices and the memory control logic.

17. The method of claim 14, wherein the non-volatile memory is implemented in a plurality of memory devices including memory cells, wherein a controller external to the memory devices generates the instances of the command, wherein component logic on the memory devices having the memory cells to erase executes the instances of the command, and wherein to perform the at least one read or write operation and to determine whether the block erase operation completed are performed by the component logic.

18. A system, comprising:

a processor executing program code that generates read and write operations;

a storage device, comprising;

a non-volatile memory; and

memory control logic to;

generate a command to perform a portion of a block erase operation with respect to a block a block, wherein the block comprises a block of pages in the non-volatile memory for a block erase operation for the block;

perform at least one read or write operation with respect to a page from the processor executing the program code after executing the command; and

execute an additional instance of the command to perform an additional portion of the block erase operation with respect to the block in response to determining that the block erase operation of the block did not complete after performing the at least one read or write operation, wherein each of multiple instances of the command are interleaved with read or write operations by generating each of the instances of the command between a plurality of read or write operations until the block erase operation completes, wherein interleaving the instances of the command limits a number of the write operations before executing the command so that the block is successfully erased by a time a block of pages is written.

19. The system of claim 18, wherein to generate the instances of the command and to perform the at least one read or write operation from the processor comprises interleaving the at least one read or write operation with the instances of the command until the block erase operation for the block completes.

20. The system of claim 18, wherein the command is executed to perform a pulse and verify operation to apply a pulse of voltage to cells subject to the portion of the block erase operation and to verify whether the cells subject to the block erase operation are in an erased state.