Semiconductor device and method including an intertial mass element

• US 9,679,857 B2
• Filed: 09/15/2016
• Issued: 06/13/2017
• Est. Priority Date: 07/15/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: van Dal, Mark, Merz, Matthias, Ponomarev, Youri Victorovitch
• Primary Examiner(s): Rodela, Eduardo A
• Assistant Examiner(s): Roland, Christopher M
• Application Number:
  US15/266,809
• Publication Number:
  US 20170005045A1
• Time in Patent Office: 271 Days
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/013 Etching
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 99/005 Test apparatus
• CPC Class Codes: G01P 15/06 using members subjected to a permanent deformation
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0862 being provided with particular means being integrated into a MEMS accelerometer structure for providing particular additional functionalities to those of a spring mass system
• CPC Class Codes: G01P 2015/0877 using integrated interconnect structures
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26

Abstract

Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure and a second conductive support structure and a cavity in which an inertial mass element comprising at least one metal portion is conductively coupled to the first support structure and the second support structure by respective conductive connection portions, at least one of said conductive connection portions being designed to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by the dimensions of the conductive connection portions. A method of manufacturing such a semiconductor device is also disclosed.

Claims

1. A semiconductor device comprising:

a stack of patterned metal layers separated by dielectric layers, the dielectric layers having a first plurality of conductive vias that connect metal layers adjacent to the dielectric layers, the stack comprising;

a first conductive support structure having a first metal layer and a second conductive support structure having a second metal layer;

a cavity between the first conductive support structure and the second conductive support structure;

an inertial mass element having at least one metal portion which is vertically displaced with respect to the first metal layer and the second metal layer; and

a first plurality of conductive connection vias that conductively couple the inertial mass element to the first metal layer and the second metal layer, wherein at least one of the first plurality of conductive connection vias is configured to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by dimensions of the first plurality of conductive connection vias.

2. The semiconductor device of claim 1, further comprising:

a detector configured to detect a disruption in the conductive coupling of the inertial mass element to the first metal layer and the second metal layer.

3. The semiconductor device of claim 1, wherein the inertial mass element is below the first metal layer and the second metal layer.

4. The semiconductor device of claim 1, wherein the inertial mass element is above the first metal layer and the second metal layer.

5. The semiconductor device of claim 4, wherein the first plurality of vias connect the inertial mass element to the first metal layer and the second metal layer near a first lateral end of the inertial mass element and a first force applied to a second lateral end of the inertial mass element applies a second force to one of the first plurality of vias in a substantially opposite direction of the applied first force.

6. The semiconductor device of claim 1, wherein the inertial mass element is between the first metal layer and the second metal layer.

7. The semiconductor device of claim 1, wherein the inertial mass element has a plurality of perforations extending through the inertial mass element.

8. The semiconductor device of claim 1, wherein the inertial mass element comprises a stack of metal layer portions separated by dielectric layer portions and each of the dielectric layer portions comprises a second plurality of vias configured to conductively interconnect the stack of metal layer portions.

9. The semiconductor device of claim 1, wherein the stack comprises a plurality of cavities each comprising a respective inertial mass element conductively coupled to the first metal layer and the second metal layer by the first plurality of vias and at least one of the first plurality of vias associated respectively with each cavity is configured to break upon the respective inertial mass element being exposed to an acceleration force exceeding a threshold that is unique to that respective cavity.

10. A method of manufacturing a semiconductor device, comprising:

forming a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure having a first metal layer, a second conductive support structure having a second metal layer, and an inertial mass element comprising at least one metal portion and a first plurality of conductive connection vias that conductively couple the inertial mass element to the first metal layer and the second metal layer, wherein at least one of the first plurality of conductive connection vias is configured to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by dimensions of the first plurality of conductive connection vias;

forming a passivation layer over the stack;

selectively removing the passivation layer over an area comprising the inertial mass element to form an exposed area; and

etching the exposed area to form a cavity around the inertial mass element.

11. The method of claim 10, wherein the stack comprises a perforated metal portion extending over the inertial mass element and at least partially extending over the first conductive support structure and the second conductive support structure and the etching step is performed through perforations of the perforated metal portion.