Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material

• US 9,679,881 B2
• Filed: 09/09/2013
• Issued: 06/13/2017
• Est. Priority Date: 02/03/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Chua, Linda Pei Ee, Pagaila, Reza A., Do, Byung Tai
• Primary Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US14/021,206
• Publication Number:
  US 20140008769A1
• Time in Patent Office: 1,373 Days
• Field of Search: 257E23128, 257E23129, 257E23134, 257414-470, 257777, 257787, 257788, 257680, 257E23001, 257E23002, 257E3111, 257E31117, 257E3113, 257E23116, 257E23123, 257E23194, 257E21502, 257E21503, 257E23169, 438 22, 438 25, 438 28, 438 33, 438 48- 98, 438110-113, 438116, 438117, 438127, 438455, 438456, 438458, 438759
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Claims

1. A method of making a semiconductor device, comprising:

providing a build-up interconnect structure including a plurality of insulating layers interleaved with a plurality of conductive layers;

disposing a plurality of first conductive bumps on a bottom surface of the build-up interconnect structure;

disposing a first semiconductor die on a top surface of the build-up interconnect structure with an active surface of the first semiconductor die oriented away from the build-up interconnect structure and an adhesive layer between the build-up interconnect structure and first semiconductor die;

forming a bond wire extending from a first contact pad on the active surface of the first semiconductor die to the top surface of the build-up interconnect structure;

disposing a second conductive bump on a second contact pad on the active surface of the first semiconductor die;

providing a semiconductor wafer including a plurality of second semiconductor die including an active surface of each of the plurality of second semiconductor die comprising a stress sensitive region including a plurality of integrated passive devices (IPDs) for high frequency signal processing;

depositing an underfill material on the active surfaces of the second semiconductor die while using a mask or screen disposed over the stress sensitive regions of the second semiconductor die to prevent the underfill material from extending onto the stress sensitive regions of the second semiconductor die;

singulating the semiconductor wafer through the underfill material to separate the second semiconductor die;

disposing one of the second semiconductor die over the first semiconductor die and build-up interconnect structure with the active surface and stress sensitive region of the second semiconductor die oriented toward the first semiconductor die;

pressing the second conductive bump on the first semiconductor die into the underfill material on the second semiconductor die to bring the second conductive bump into contact with a third contact pad on the active surface of the second semiconductor die, wherein the underfill material provides an air gap between the first semiconductor die and the stress sensitive region of the second semiconductor die; and

depositing an encapsulant over the build-up interconnect structure to fully cover the first semiconductor die, second semiconductor die, and bond wire, wherein side surfaces of the encapsulant are coplanar with side surfaces of the build-up interconnect structure.

2. The method of claim 1, further including providing the second conductive bump as one of a plurality of stacked stud bumps.

3. The method of claim 1, further including forming a plurality of through-silicon vias (TSV) through the first semiconductor die.

4. The method of claim 1, wherein pressing the second conductive bump between the first semiconductor die and second semiconductor die comprises compression bonding the second conductive bump to the third contact pad.

5. The method of claim 1, further including preventing the underfill material from extending onto the stress sensitive regions of the second semiconductor die by:

disposing a screen over the stress sensitive regions; and

using a squeegee to dispense the underfill material over areas of the semiconductor wafer not covered by the screen.

6. The method of claim 1, further including preventing the underfill material from extending over the stress sensitive regions of the second semiconductor die by:

forming a mask directly on the stress sensitive regions;

depositing the underfill material over the second semiconductor die around the mask; and

removing the mask to leave a cavity in the underfill material.

7. A method of making a semiconductor device, comprising:

providing a build-up interconnect structure;

disposing a first semiconductor die over the build-up interconnect structure with an active surface of the first semiconductor die oriented away from the build-up interconnect structure;

forming a bond wire extending from the active surface of the first semiconductor die to a top surface of the build-up interconnect structure;

disposing a conductive bump on the active surface of the first semiconductor die;

providing a semiconductor wafer including a plurality of second semiconductor die including a stress sensitive region of each of the second semiconductor die comprising a plurality of integrated passive devices (IPDs) for high frequency signal processing;

depositing an underfill material over the semiconductor wafer while using a mask or screen disposed over the stress sensitive regions of the second semiconductor die to prevent the underfill material from extending over the stress sensitive regions of the second semiconductor die;

singulating the semiconductor wafer through the underfill material to separate the second semiconductor die;

disposing one of the second semiconductor die over the first semiconductor die and build-up interconnect structure with the stress sensitive region of the second semiconductor die oriented toward the first semiconductor die;

pressing the conductive bump on the first semiconductor die into the underfill material on the second semiconductor die to bring the conductive bump into contact with the second semiconductor die, wherein a cavity of the underfill material provides an air gap between the first semiconductor die and the stress sensitive region of the second semiconductor die; and

depositing an encapsulant over the build-up interconnect structure, first semiconductor die, and second semiconductor die, wherein side surfaces of the encapsulant are coplanar with side surfaces of the build-up interconnect structure.

8. The method of claim 7, further including providing the conductive bump as one of a plurality of stacked stud bumps.

9. The method of claim 7, further including forming a plurality of through-silicon vias (TSV) through the first semiconductor die.

10. The method of claim 7, wherein pressing the conductive bump between the first semiconductor die and second semiconductor die comprises compression bonding the conductive bump to the second semiconductor die.

11. The method of claim 7, further including preventing the underfill material from extending over the stress sensitive regions of the second semiconductor die by:

disposing a screen over the stress sensitive regions; and

using a squeegee to dispense the underfill material onto areas of the semiconductor wafer not covered by the screen.

12. The method of claim 7, further including preventing the underfill material from extending over the stress sensitive regions of the second semiconductor die by:

forming a mask directly on the stress sensitive regions;

depositing the underfill material over the second semiconductor die around the mask; and

removing the mask to leave a cavity in the underfill material.

13. The method of claim 7, further including providing the IPDs to include a capacitor and an inductor for radio frequency (RF) signal processing.

14. A method of making a semiconductor device, comprising:

providing an interconnect structure;

disposing a first semiconductor die over the interconnect structure with an active surface of the first semiconductor die oriented away from the interconnect structure;

disposing a conductive bump on the active surface of the first semiconductor die;

depositing an underfill material over the first semiconductor die and contacting the bump while using a mask or screen to form a cavity in the underfill material over a portion of the first semiconductor die;

providing a second semiconductor die including a stress sensitive region of the second semiconductor die comprising a plurality of integrated passive devices (IPDs) for high frequency signal processing;

disposing the second semiconductor die over the first semiconductor die and interconnect structure with the stress sensitive region of the second semiconductor die aligned with the cavity in the underfill material and the conductive bump contacting the second semiconductor die; and

depositing an encapsulant over the interconnect structure, first semiconductor die, and second semiconductor die, wherein a surface of the encapsulant is coplanar with a surface of the interconnect structure.

15. The method of claim 14, further including providing the conductive bump as one of a plurality of stacked stud bumps.

16. The method of claim 14, further including forming a plurality of through-silicon vias (TSV) through the first semiconductor die.

17. The method of claim 14, wherein pressing the conductive bump between the first semiconductor die and second semiconductor die comprises compression bonding the conductive bump to the second semiconductor die.

18. The method of claim 14, further including preventing the underfill material from extending over the portion of the first semiconductor die by:

disposing a screen over the portion of the first semiconductor die; and

using a squeegee to dispense the underfill material over areas of the first semiconductor die not covered by the screen.

19. The method of claim 14, further including preventing the underfill material from extending over the portion of the first semiconductor die by:

forming a mask directly on the first semiconductor die;

depositing the underfill material over the first semiconductor die around the mask; and

removing the mask.

20. The method of claim 14, further including providing the IPDs to include a capacitor and an inductor for radio frequency (RF) signal processing.