Pads and pin-outs in three dimensional integrated circuits

• US 9,679,914 B2
• Filed: 05/18/2015
• Issued: 06/13/2017
• Est. Priority Date: 10/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US14/715,375
• Publication Number:
  US 20160013192A1
• Time in Patent Office: 757 Days
• Field of Search: 257209, 257686, 257E29001, 257E21001, 438128
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Claims

1. A semiconductor device, comprising:

a first layer including a pattern of metal layers associated with a predetermined functionality for the semiconductor device;

a second layer including a plurality of programmable circuits; and

a third layer including a plurality of pads and a plurality of wire interconnects that pass through a third layer boundary and extend into at least one of the first layer or the second layer, wherein the first layer, the second layer, and the third layer form a stack;

wherein the pattern of metal layers is configured to hard-wire the plurality of programmable circuits with the predetermined functionality.

2. The semiconductor device of claim 1, wherein a first portion of the pattern of metal layers is operable to couple to a logic high source, and wherein a second portion of the pattern of metal layers is operable to couple to a logic low source.

3. The semiconductor device of claim 1, wherein the second layer further comprises a plurality of input/output circuits operable to couple by the plurality of wire interconnects to the plurality of pads, which are operable to electrically connect the semiconductor device to an external device and which are electrically connectable by a portion of the plurality of wire interconnects via the second layer to the pattern of metal layers.

4. The semiconductor device of claim 1, wherein the first layer is below the second layer and the third layer.

5. The semiconductor device of claim 1, wherein the second layer is below the first layer and the third layer.

6. The semiconductor device of claim 1, further comprising a fourth layer including a plurality of metal interconnects.

7. The semiconductor device of claim 6, wherein the fourth layer is disposed between the first layer and the second layer.

8. A method, comprising:

forming a semiconductor device, wherein said forming a semiconductor device comprises;

forming a stack including;

a first layer comprising a pattern of metal layers associated with a predetermined functionality for the semiconductor device;

a second layer comprising a plurality of programmable circuits; and

a third layer comprising a plurality of pads and a plurality of wire interconnects that pass through a third layer boundary and extend into at least one of the first layer or the second layer;

wherein the pattern of metal layers is configured to hard-wire the plurality of programmable circuits with the predetermined functionality; and

coupling at least a portion of the plurality of pads to the second layer.

9. The method of claim 8, wherein a first portion of the pattern of metal layers is operable to couple to a logic high source, and wherein a second portion of the pattern of metal layers is operable to couple to a logic low source.

10. The method of claim 8, wherein the second layer further comprises a plurality of input/output circuits operable to couple by the plurality of wire interconnects to the plurality of pads, which are operable to electrically connect the semiconductor device to an external device and which are electrically connectable by a portion of the plurality of wire interconnects via the second layer to the pattern of metal layers.

11. The method of claim 8, wherein the first layer is below the second layer and the third layer.

12. The method of claim 8, wherein the second layer is below the first layer and the third layer.

13. The method of claim 8, wherein the stack further comprises a fourth layer including a plurality of metal interconnects.

14. The method of claim 13, wherein the fourth layer is disposed between the first layer and the second layer.

15. A semiconductor device, comprising:

a substrate including a plurality of programmable circuits;

a first layer including a pattern of metal layers associated with a predetermined functionality for the semiconductor device; and

a second layer including a plurality of pads and a plurality of wire interconnects that pass through a second layer boundary and extend into at least one of the substrate or the first layer, wherein the substrate, the first layer, and the second layer form a stack;

wherein the pattern of metal layers is configured to hard-wire the plurality of programmable circuits with the predetermined functionality.

16. The semiconductor device of claim 15, wherein a first portion of the pattern of metal layers is operable to couple to a logic high source, and wherein a second portion of the pattern of metal layers is operable to couple to a logic low source.

17. The semiconductor device of claim 15, wherein the substrate further comprises a plurality of input/output circuits operable to couple by the plurality of wire interconnects to the plurality of pads, which are operable to electrically connect the semiconductor device to an external device and which are electrically connectable by a portion of the plurality of wire interconnects via the substrate to the pattern of metal layers.

18. The semiconductor device of claim 15, further comprising a third layer including a plurality of metal interconnects.

19. The semiconductor device of claim 18, wherein the third layer is disposed between the substrate and the first layer.

20. The semiconductor device of claim 15, further comprising a heat sink coupled to the substrate.