Trench MOSFET shield poly contact

• US 9,680,003 B2
• Filed: 03/27/2015
• Issued: 06/13/2017
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: De Fresart, Edouard D., Qin, Ganming, Ku, Pon Sung, Petras, Michael F., Zitouni, Moaniss, Zupac, Dragan
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US14/671,590
• Publication Number:
  US 20160284838A1
• Time in Patent Office: 809 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Claims

1. A device comprising:

a plurality of vertical transistors at a semiconductor layer coupled together in parallel residing within an outer perimeter of a recessed region of a semiconductor layer, each vertical transistor comprising a mesa having a channel region and being spaced apart from corresponding adjacent mesas in a transverse direction by a first dimension, each corresponding mesa spaced apart from the outer perimeter in a lateral direction by approximately the first dimension;

each adjacent mesa pair associated with a point that is equidistant from an end of each mesa of the adjacent mesa pair and from the outer perimeter in the lateral direction; and

a plurality of inter-level conductive plugs connected to a shield terminal electrode and to a device shield within the recessed region, each point being associated with a corresponding mesa pair and located within a perimeter of a corresponding one of the plurality of conductive plugs.

2. The device of claim 1, wherein between each mesa of each of the mesa pairs there is an active gate corresponding to channel regions of each mesa, and an active shield portion of the device shield.

3. The device of claim 2, wherein the device shield further comprises a termination shield that is concentric to the outer perimeter, and each end of a plurality of active shields is connected to opposing sides of the termination shield.

4. The device of claim 3, wherein a transverse dimension each conductive plug is equal to or less than a transverse dimension of a width of the active shield.

5. The device of claim 4, wherein each conductive plug is spaced apart from all edges of the device shield by a dimension that is at least one-half of a lateral dimension of the conductive plug.

6. The device of claim 1, wherein each conductive plug is spaced apart from all edges of the device shield by a dimension that is at least one-half of a lateral dimension of the conductive plug.

7. The device of claim 1, wherein the device shield further comprises a termination shield that is concentric to the outer perimeter, and each end of a plurality of active shields is connected to opposing sides of the termination shield.

8. The device of claim 1, wherein approximately the first dimension is +/−

25% of the first dimension.

9. The device of claim 1, wherein approximately the first dimension is +/−

10% of the lateral dimension of the conductive plugs.

10. The device of claim 1, wherein approximately the first dimension is based upon a manufacturing tolerance of a process used to manufacture the device.

11. The device of claim 1, wherein each conductive plug has a minimum diameter and a center location, and each point is within an offset dimension of the center location of its corresponding conductive plug, wherein the offset dimension is approximately 25% of the minimum diameter.

12. The device of claim 1, wherein each conductive plug has a minimum diameter and a center location, and each point is within an offset dimension of the center location of its corresponding conductive plug, wherein the offset dimension is at least 10% of the minimum diameter.

13. A device comprising:

a semiconductor layer comprising a first major surface and a second major surface;

a plurality of mesa structures of the semiconductor layer defined by a recess of the semiconductor layer, the recess having an outer perimeter;

each mesa structure comprising

two lateral major sides and two minor sides, from a plan view, each major side having a first dimension, each minor side having a second dimension, the first dimension being at least twice the second dimension;

a first source/drain region;

a channel region, the channel region being further from the first major surface than the first source drain region

from the plan view, each pair of adjacent mesas comprises

a transverse spacing between mesas of the pair that is a third dimension, a lateral spacing between an end of each mesa and a proximal location of the outer perimeter that is a fourth dimension, the third and fourth dimensions being substantially the same dimension;

from the plan view, each pair of mesas defines a trench region of the recess comprising an active trench and a termination trench, the active trench residing between the pair of mesas, and the termination trench residing in a lateral direction between the end of each mesa and their corresponding active trench and the perimeter;

each trench region comprising

an active portion of a shield electrode that resides at the active trench of the trench region, and a termination portion residing at the termination trench of the trench region; and

a control electrode between the first major surface and a shield region to control a conductivity state of the channel region of each mesa of pair of mesas corresponding to the trench;

a shield termination electrode;

each shield electrode'"'"'s termination region connected to a corresponding conductive plug that is further connected to a shield runner, and from the plan view, a perimeter of the conductive plug includes a point that is equidistant to an end of each mesa corresponding to the shield electrodes'"'"' pair of mesas and a proximal side of the outer perimeter.

14. The device of claim 13, wherein each mesa structure further comprises a second source/drain, wherein the channel region is between the first and second source/drain.