Semiconductor device having an active trench and a body trench

• US 9,680,005 B2
• Filed: 08/12/2015
• Issued: 06/13/2017
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wolter, Frank, Niedernostheide, Franz-Josef, Gawlina-Schmidl, Yvonne, Cotorogea, Maria, Schulze, Hans-Joachim
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/824,388
• Publication Number:
  US 20150349116A1
• Time in Patent Office: 671 Days
• Field of Search: 257139, 257320, 257330-334, 257329, 257E2141, 257E27091, 438270, 438271, 438587, 438588
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Claims

1. A semiconductor device formed in a semiconductor substrate including a first main surface, comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type, the body region being disposed between the drift region and the first main surface;

a first transistor cell and a second transistor cell, each of the first and second transistor cells comprising

an active trench at the first main surface and extending into the drift region;

a gate conductive layer disposed in the active trench; and

a source region formed in the body region adjacent to the active trench,

the semiconductor device further comprising a first body trench and a second body trench between the first and the second transistor cells, the first and second body trenches being formed in the first main surface and extending into the drift region, the first and second body trenches being adjacent to the body region and the drift region, a conductive material in at least one of the first and second body trenches being connected with a gate terminal, at least one of the first and second body trenches being different from the active trench in shape, material(s) inside the trench or functionality.

2. The semiconductor device of claim 1, wherein the conductive material in at least one of the first and second body trenches is connected with the source terminal.

3. The semiconductor device of claim 2, wherein the conductive material in another of the first and second body trenches is connected with the gate terminal.

4. The semiconductor device of claim 3, wherein a distance between one of the first and second body trenches being connected with the source terminal and the active trench is smaller than a distance between one of the body trenches being connected with the gate terminal and the active trench.

5. The semiconductor device of claim 1, wherein the conductive material in all of the first and second body trenches is connected with the gate terminal.

6. The semiconductor substrate of claim 1, further comprising a gate dielectric layer at sidewalls and at a bottom side of the active trench, wherein a thickness of the gate dielectric layer is smaller than a thickness of the insulating layer in at least one of the first and second body trenches.

10. The semiconductor device of claim 1, wherein the first body trench is disposed adjacent to the second body trench.

7. A semiconductor device formed in a semiconductor substrate including a first main surface, comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type, the body region being disposed between the drift region and the first main surface;

a first transistor cell and a second transistor cell, each of the first and second transistor cells comprising

an active trench at the first main surface and extending into the drift region;

a gate conductive layer disposed in the active trench; and

a source region formed in the body region adjacent to the active trench,

the semiconductor device further comprising body trenches disposed between the first and the second transistor cells, the body trenches being formed in the first main surface and extending into the drift region, the body trenches being adjacent to the body region and the drift region, wherein a conductive material in all of the body trenches is connected with the gate terminal.

8. The semiconductor device of claim 7, wherein at least one of the body trenches is different from the active trench.

9. The semiconductor device of claim 7, further comprising a gate dielectric layer at sidewalls and at a bottom side of the active trench, wherein a thickness of the gate dielectric layer is smaller than a thickness of the insulating layer in at least one of the body trenches.