Passivated and faceted fin field effect transistor

• US 9,680,021 B2
• Filed: 02/08/2016
• Issued: 06/13/2017
• Est. Priority Date: 10/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shih, Chi-Yuan, Liu, Chi-Wen, Chen, Yen-Yu
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US15/018,245
• Publication Number:
  US 20160155846A1
• Time in Patent Office: 491 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Claims

1. A fin field effect transistor (FinFET) comprising:

a substrate;

a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant than an immediately underlying layer, wherein the one or more semiconductor layers comprises a first semiconductor layer, the first semiconductor layer being a first silicon germanium layer;

an isolation region adjacent opposing sidewalls of the fin structure, the fin structure having an upper portion extending above the isolation region, the upper portion having slanted sidewalls;

a first passivation layer interposed between the fin structure and the isolation region;

a second passivation layer on the upper portion of the fin structure, wherein the second passivation layer extends over sidewalls and an upper surface of the first semiconductor layer, the second passivation layer being a silicon germanium oxynitride layer; and

a gate structure overlying the upper portion of the fin structure.

2. The FinFET of claim 1, wherein the fin structure comprises a second silicon germanium layer over the first silicon germanium layer, wherein a lattice constant of the first silicon germanium layer differs from a lattice constant of the second silicon germanium layer.

3. The FinFET of claim 2, wherein the isolation region extends to an interface between the first silicon germanium layer and the second silicon germanium layer.

4. The FinFET of claim 1, wherein the first passivation layer comprises an oxynitride.

5. The FinFET of claim 1, wherein an interface between the first passivation layer and the second passivation layer is aligned with an upper surface of the isolation region.

6. The FinFET of claim 1, wherein the first semiconductor layer is an uppermost semiconductor layer of the fin structure.

7. The FinFET of claim 1, wherein the first semiconductor layer has a thickness from about 10 nm to about 50 nm.

8. The FinFET of claim 7, wherein the first semiconductor layer has a width of 6 nm to 20 nm.

9. The FinFET of claim 1, wherein the silicon germanium oxynitride layer has a ratio of y:

x in SiGeO_xN_y between 0.25 to 0.9.

10. A fin field effect transistor (FinFET) comprising:

a substrate having a fin structure, the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant of an immediately underlying layer, the fin structure having a lower portion and an upper portion;

an isolation region adjacent opposing sidewalls of the fin structure, an upper surface of the isolation region being level with a junction between the upper portion and the lower portion, sidewalls of the upper portion immediately above the junction being slanted relative to sidewalls of a portion of the fin structure immediately below the junction;

a first passivation layer interposed between the fin structure and the isolation region;

a second passivation layer on the upper portion of the fin structure; and

a gate structure overlying the upper portion of the fin structure.

11. The FinFET of claim 10, wherein the fin structure comprises a silicon germanium layer over a silicon substrate, and a germanium layer over the silicon germanium layer.

12. The FinFET of claim 10, wherein the fin structure comprises a silicon germanium layer over a silicon substrate.

13. The FinFET of claim 10, wherein the fin structure comprises a first silicon germanium layer over a silicon substrate, and a second silicon germanium layer over the first silicon germanium layer, wherein a relative concentration of germanium in the first silicon germanium layer differs from a relative concentration of germanium in the second silicon germanium layer.

14. The FinFET of claim 10, wherein the upper portion comprises a single semiconductor layer of the one or more semiconductor layers.

15. A fin field effect transistor (FinFET) comprising:

a fin structure comprising one or more semiconductor layers, each semiconductor layer of the one or more semiconductor layers having a different lattice constant of a corresponding immediately underlying semiconductor layer of the one or more semiconductor layers, the fin structure having a lower portion and an upper portion, the one or more semiconductor layers comprising a first semiconductor layer and a second semiconductor layer immediately underlying the first semiconductor layer, sidewalls of the first semiconductor layer immediately adjacent an interface between the first semiconductor layer and the second semiconductor layer being slanted relative to sidewalls of the second semiconductor layer;

a first passivation layer along sidewalls of the lower portion of the fin structure;

an isolation region over the first passivation layer along opposing sidewalls of the fin structure;

a second passivation layer on sidewalls of the upper portion of the fin structure, an interface between the first passivation layer and the second passivation layer being aligned with an upper surface of the isolation region;

a gate dielectric layer over the second passivation layer; and

a gate electrode over the gate dielectric layer.

16. The FinFET of claim 15, wherein the first passivation layer comprises a first oxynitride, the second passivation layer comprises a second oxynitride.

17. The FinFET of claim 15, wherein a lowermost semiconductor layer of the one or more semiconductor layers comprises a portion of an underlying semiconductor substrate.

18. The FinFET of claim 15, wherein the first passivation layer completely covers sidewalls of a semiconductor layer next to an uppermost semiconductor layer of the one or more semiconductor layers.

19. The FinFET of claim 15, wherein sidewalls of the upper portion of the fin structure have a lower slope than sidewalls of the lower portion of the fin structure, an interface between the lower portion and the upper portion being aligned with an upper surface of the isolation region.

20. The FinFET of claim 15, wherein the first semiconductor layer is an uppermost semiconductor layer.