Ground fault circuit interrupter and method

• US 9,680,421 B2
• Filed: 04/19/2016
• Issued: 06/13/2017
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Beck, Riley D., Layton, Kent D.
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Curtis, Sean
• Application Number:
  US15/132,775
• Publication Number:
  US 20160233837A1
• Time in Patent Office: 420 Days
• Field of Search: 324509
• CPC Class Codes: G01R 27/18 Measuring resistance to earth , i.e. line to ground
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: H02H 1/0092 concerning the data processing means, e.g. expert systems, neural networks
• CPC Class Codes: H02H 1/04 Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks
• CPC Class Codes: H02H 3/162 for ac systems
• CPC Class Codes: H02H 3/33 using summation current transformers H02H3/347 takes precedence
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 2203/45152 Balancing means being added at the input of a dif amp to reduce the offset of the dif amp
• CPC Class Codes: H03F 2203/45228 A transformer being added at the output or the load circuit of the dif amp
• CPC Class Codes: H03F 2203/45288 Differential amplifier with circuit arrangements to enhance the transconductance
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062

Abstract

A method and circuit for dynamically correcting offsets associated with an AC power system. In an embodiment, a first offset current generated in response to a ground to neutral fault stimulus is decreased and a second offset current generated in response to a differential fault stimulus is decreased. In another embodiment, the circuit includes an offset correction circuit that has one of a chopper circuit or an auto-zeroing circuit. An amplifier is connected to the offset correction circuit and an output connected to the offset correction circuit. A signal generator is switchably coupled to a first input of the offset correction circuit and a bias generator is switchably coupled to the first input of the offset correction circuit.

Claims

1. A device configured to dynamically correct offsets associated with an AC power system that includes a line conductor, a neutral conductor, and a transformer, the device comprising:

an offset correction circuit having first and second inputs and first and second outputs, the offset correction circuit comprising one of a chopper circuit or an auto-zeroing circuit;

a first amplifier having first and second inputs and an output, the first and second inputs coupled to the first and second outputs of the offset correction circuit, respectively, and the output of the amplifier coupled to the second input of the offset correction circuit;

a signal generator switchably coupled to the first input of the offset correction circuit; and

a bias generator switchably coupled to the first input of the offset correction circuit.

2. The device of claim 1, further including a switch coupled between the first input of the offset correction circuit and the signal generator and between the first input of the offset correction circuit and the bias generator.

3. The device of claim 2, wherein the offset correction circuit comprises the chopper circuit.

4. The device of claim 1, wherein the chopper circuit comprises:

a first differential pair of transistors having first and second control electrodes, first and second current carrying electrodes, and a common electrode;

a first switching network coupled between the first control electrode of the first differential pair of transistors and the first input of the offset correction circuit; and

a second switching network coupled between the second control electrode of the first pair differential pair of transistors and the second input of the offset correction circuit.

5. The device of claim 4, wherein the first switching network comprises:

a first switch having a control terminal, a first conduction terminal, and a second conduction terminal, the first conduction terminal of the first switch coupled to the control electrode of the first differential pair of transistors, the second conduction terminal of the first switch coupled to the first input of the offset correction circuit, and the control terminal of the first switch coupled to a third input of the offset correction circuit; and

a second switch having a control terminal, a first conduction terminal, and a second conduction terminal, the first conduction terminal of the second switch coupled to the first control electrode of the first differential pair of transistors and to the first conduction terminal of the first switch, the second conduction terminal of the second switch coupled to the second input of the offset correction circuit, and the control terminal of the second switch coupled to a fourth input of the offset correction circuit.

6. The device of claim 5, wherein the second switching network comprises:

a third switch having a control terminal, a first conduction terminal, and a second conduction terminal, the first conduction terminal of the third switch coupled to the second control electrode of the first differential pair of transistors, the second conduction terminal of the third switch coupled to the second input of the offset correction circuit and to the second conduction terminal of the second switch, and the control terminal of the third switch coupled to the third input of the offset correction circuit; and

a fourth switch having a control terminal, a first conduction terminal, and a second conduction terminal, the first conduction terminal of the fourth switch coupled to the second control electrode of the first differential pair of transistors and to the first conduction terminal of the third switch, the second conduction terminal of the fourth switch coupled to the first input of the offset correction circuit and to the second conduction terminal of the first switch, and the control terminal of the second switch coupled to the fourth input of the offset correction circuit.

7. The device of claim 5, further including:

a first current source coupled to the common electrode of the first pair of differential transistors;

a second current source coupled to the first current carrying electrode of the first pair of differential transistors; and

a third current source coupled to the second current carrying electrode of the first pair of differential transistors.

8. The device of claim 6, wherein the chopper circuit further comprises:

a second differential pair of transistors having first and second control electrodes and first and second current carrying electrodes, the first and second control electrodes coupled together, the first current carrying electrode of the second pair of differential transistors coupled to the first current carrying electrode of the first differential pair of transistors and the second current carrying electrode of the second pair of differential transistors coupled to the second current carrying electrode of the first differential pair of transistors; and

a third switching network coupled to the first and second current carrying electrodes of the second differential pair of transistors.

9. The device of claim 8, wherein the third switching network comprises:

a fifth switch having a control terminal, a first conduction terminal, and a second conduction terminal, the control terminal of the fifth switch coupled to the control terminal of the first switch, to the control terminal of the third switch, and to the third input of the offset correction circuit, the first conduction terminal of the fifth switch coupled to the first current carrying terminal of the second differential pair of transistors; and

a sixth switch having a control terminal, a first conduction terminal, and a second conduction terminal, the control terminal of the sixth switch coupled to the control terminal of the second switch, to the control terminal of the fourth switch, and to the fourth input of the offset correction circuit, the first conduction terminal of the sixth switch coupled to the first conduction terminal of the fifth switch to form an output of the chopper circuit, and the second conduction terminal of the sixth switch coupled to the second current carrying terminal of the second differential pair of transistors.

10. The device of claim 9, further including:

a seventh switch having a control terminal, a first conduction terminal, and a second conduction terminal, the control terminal of the seventh switch coupled to the control terminal of the first switch, to the control terminal of the third switch, to the control terminal of the fifth switch, and to the third input of the offset correction circuit, the first conduction terminal of the seventh switch coupled to the first current carrying terminal of the second differential pair of transistors and the second conduction terminal of the seventh switch coupled to the first and second control electrodes of the second pair of differential transistors; and

an eighth switch having a control terminal, a first conduction terminal, and a second conduction terminal, the control terminal of the eighth switch coupled the control terminal of the sixth switch, coupled to the control terminal of the second switch, coupled to the control terminal of the fourth switch, and coupled to the fourth input of the offset correction circuit, first conduction terminal of the eighth switch coupled to the second current carrying terminal of the second differential pair of transistors and the second conduction terminal of the eighth switch coupled to the first and second control electrodes of the second pair of differential transistors and to the second conduction terminal of the seventh switch.

11. The device of claim 10, further including:

a first transistor having a control electrode, a first current carrying electrode, and a second current carrying electrode, the control electrode of the first transistor coupled for receiving a bias voltage, the first current carrying electrode of the first transistor coupled to the first current carrying electrode of the second differential pair, and the second current carrying electrode of the first transistor coupled to the second current source; and

a second transistor having a control electrode, a first current carrying electrode, and a second current carrying electrode, the control electrode of the second transistor coupled for receiving a bias voltage, the first current carrying electrode of the second transistor coupled to the second current carrying electrode of the second differential pair, and the second current carrying electrode of the second transistor coupled to the third current source.

12. The device of claim 1, wherein the bias generator comprises a second amplifier having first and second inputs and an output, the first input of the second amplifier coupled to output of the second amplifier and the second input of the second amplifier coupled for receiving a bias voltage.

13. The device of claim 1, wherein the offset correction circuit comprises the auto-zeroing circuit.

14. A device configured to dynamically correct offsets associated with an AC power system that includes a line conductor, a neutral conductor, and a transformer, the device comprising:

an offset correction circuit having a plurality of input terminals and a plurality of output terminals, the offset correction circuit comprising one of a chopper circuit or an auto-zeroing circuit;

a first amplifier having first and second inputs and a plurality of outputs, the first and second inputs coupled to first and second output terminals of the plurality of output terminals of the offset correction circuit, respectively, and a first output of the plurality of outputs of the amplifier coupled to a first input of the plurality of input terminals of the offset correction circuit;

a first switch having a control terminal, a first conduction terminal, a second conduction terminal, and a third conduction terminal, the first conduction terminal coupled to the a second input terminal of the plurality of input terminals of the offset correction circuit;

a signal generator coupled to the second conduction terminal of the first switch;

a bias generator coupled to the third conduction terminal of the first switch;

a first detector having an input terminal and an output terminal, the input terminal of the first detector coupled to a second output of the plurality of outputs of the first amplifier; and

a control circuit having a plurality of inputs and a plurality of outputs, a first output of the plurality of outputs of the control circuit coupled to the control terminal of the first switch.

15. The device of claim 14, wherein the control circuit is a digital control circuit having a second output of the plurality of outputs of the control circuit coupled to a third input terminal of the plurality of input terminals of the offset correction circuit, a third output of the plurality of outputs of the control circuit coupled to a fourth input of the plurality of input terminals of the offset correction circuit, and a fourth output of the plurality of outputs of the control circuit coupled to the signal generator.