Digital circuits having improved transistors, and methods therefor

• US 9,680,470 B2
• Filed: 09/28/2015
• Issued: 06/13/2017
• Est. Priority Date: 02/18/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Thompson, Scott E., Clark, Lawrence T.
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US14/867,506
• Publication Number:
  US 20160020768A1
• Time in Patent Office: 624 Days
• Field of Search: None
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Claims

1. A digital logic circuit, comprising:

a plurality of MOSFET transistors coupled by way of a plurality of controllable current paths to at least a first and second logic node to produce a predefined logic function;

wherein the plurality of transistors includes at least one precharge transistor that couples a precharge node to the first logic node in response to a first clock signal;

wherein the plurality of transistors includes at least one evaluation transistor that couples a discharge node to the second logic node in response to a second clock signal;

wherein the plurality of transistors are configured to selectively couple an output node to the first or second logic node in response to at least one input signal, the plurality of transistors having gates coupled to receive at least one input signal and source-drain paths coupled to the at least one output node;

wherein each of the plurality of transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.

2. The circuit of claim 1, wherein at least some of the plurality of transistors have a strong body coefficient sufficient to receive a bias signal to a transistor body.

3. The circuit of claim 2, wherein each of the plurality of transistors further includes a heavily doped screen layer below the blanket epitaxial layer.

4. The circuit of claim 3, wherein the digital logic circuit is configured to provide and receive signals from a static random access memory cell.

5. The circuit of claim 1, wherein each of the plurality of transistors includes a well having a preselected dopant profile, the dopant profile configured so that a predefined portion of the channel remains substantially undoped, the preselected dopant profile having a notched profile in the continuum of dopant concentration.