Apparatus for overload recovery of an integrator in a sigma-delta modulator
First Claim
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1. An apparatus comprising:
- a first integrator to receive an input signal and to generate a first output;
a second integrator to receive the first output or a version of the first output and is to generate a second output;
an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the second output;
a first digital-to-analog converter (DAC); and
a second DAC, wherein at least one of the first and second DACs is coupled to the ADC,wherein the detection circuit comprises logic to detect at least two consecutive cycles of the overload condition in the second output.
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Abstract
Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.
16 Citations
19 Claims
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1. An apparatus comprising:
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a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and is to generate a second output; an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the second output; a first digital-to-analog converter (DAC); and a second DAC, wherein at least one of the first and second DACs is coupled to the ADC, wherein the detection circuit comprises logic to detect at least two consecutive cycles of the overload condition in the second output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A sigma-delta modulator comprising:
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a loop filter having at least two integrators; an analog-to-digital converter (ADC) to quantize an output of the loop filter into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the output of the loop filter; and two digital-to-analog converters (DACs) at least one of which is coupled to the ADC, wherein the detection circuit comprises logic to detect at least two consecutive cycles of the overload condition in the second output. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A system comprising:
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an antenna; an integrated circuit (IC) coupled to the antenna, the IC including a sigma-delta modulator comprising; a loop filter having at least two integrators; and an analog-to-digital converter (ADC) to quantize an output of the loop filter into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the output of the loop filter; and a processor coupled to the IC; and at least two digital-to-analog converters (DACs), at least one of which is coupled to the ADC. - View Dependent Claims (18, 19)
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Specification