Signal recovery circuit and signal recovery method

• US 9,680,631 B2
• Filed: 07/29/2015
• Issued: 06/13/2017
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsunoda, Yukito
• Primary Examiner(s): Bello, Agustin
• Application Number:
  US14/812,281
• Publication Number:
  US 20160065316A1
• Time in Patent Office: 685 Days
• Field of Search: 398202-214
• CPC Class Codes: H04B 10/541 Digital intensity or amplitude modulation
• CPC Class Codes: H04B 10/69 Electrical arrangements in the receiver
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A signal recovery circuit includes: a data acquisition circuit configured to collect a received data signal according to a transition edge of a received signal recovery clock; and a phase adjustment circuit configured to adjust a phase relationship between the transition edge of the received signal recovery clock and the received data signal according to a data value of the received data signal to be acquired by the data acquisition circuit.

Claims

1. A signal recovery circuit comprising:

a data acquisition circuit configured to collect a received data signal according to a transition edge of a received signal recovery clock; and

a phase adjustment circuit configured to adjust a phase relationship between the transition edge of the received signal recovery clock and the received data signal according to a data value of the received data signal to be acquired by the data acquisition circuit, wherein

the phase adjustment circuit comprises a clock phase adjustment circuit configured to generate an adjustment-completed received signal recovery clock by adjusting a phase of the transition edge of the received signal recovery clock according to the data value of the received data signal to be acquired by the data acquisition circuit,

the data acquisition circuit acquires the received data signal according to the transition edge of the adjustment-completed received signal recovery clock,

the received data signal is a signal received in the form of an optical signal by direct laser modulation, and

the clock phase adjustment signal is configured to make the transition edge of the received signal recovery clock faster when the received data signal has a level of 1 and make the transition edge of the received signal recovery clock slower when the received data signal has a level of 0.

2. The signal recovery circuit according to claim 1, wherein

the clock phase adjustment circuit is an adder circuit for summing up the received signal recovery clock and the received data signal.

3. The signal recovery circuit according to claim 1, wherein

the clock phase adjustment circuit comprises a limit amplifier circuit configured to perform amplifying by limiting the strength range of an output from the adder circuit.

4. The signal recovery circuit according to claim 1, wherein

the phase adjustment circuit further comprises:

a first delay circuit configured to delay the received signal recovery clock by a first delay amount;

a second delay circuit configured to delay the received signal recovery clock by a second delay amount different from the first delay amount; and

a selector circuit configured to delay one of an output from the first delay circuit and an output from the second delay circuit according to the data value of the received data signal to be acquired by the data acquisition circuit.

5. The signal recovery circuit according to claim 1, further comprising:

a timing circuit configured to acquire an output from the data acquisition circuit according to a clock in an inverse form of the received signal recovery clock.

6. The signal recovery circuit according to claim 1, wherein

the phase adjustment circuit further comprises a data delay adjustment circuit that is configured to adjust a delay amount of the received data signal according to the data value of the received data signal to be acquired by the data acquisition circuit, wherein the data acquisition circuit acquires the received data signal whose delay amount has been adjusted at the data delay adjustment circuit according to the transition edge of the received signal recovery clock.

7. The signal recovery circuit according to claim 6, wherein

the data delay adjustment circuit is configured to delay the received data signal when the received data signal to be acquired by the data acquisition circuit has a level of 1 as compared to when it has a level of 0.

8. The signal recovery circuit according to claim 6, wherein

the data delay adjustment circuit includes:

a first delay circuit configured to delay the received data signal by a first delay amount;

a second delay circuit configured to delay the received signal recovery clock by a second delay amount different from the first delay amount; and

a selector circuit configured to delay one of an output from the first delay circuit and an output from the second delay circuit according to the data value of the received data signal to be acquired by the data acquisition circuit.

9. The signal recovery circuit according to claim 1, further comprising:

a clock and data recovery circuit (CDR) configured to recover the received signal recovery clock from the received data signal.

10. A signal recovery method comprising:

receiving an optical signal generated by direct laser modulation to generate a received data signal;

adjusting a phase relationship between a transition edge of a received signal recovery clock and the received data signal according to a data value of the received data signal;

acquiring the received data signal according to the transition edge of the received signal recovery clock;

generating an adjustment-completed received signal recovery clock by adjusting a phase of the transition edge of the received signal recovery clock according to the data value of the received data signal;

acquiring the received data signal according to the transition edge of the adjustment-completed received signal recovery clock;

making the transition edge of the received signal recovery clock faster when the received data signal has a level of 1; and

making the transition edge of the received signal recovery clock slower when the received data signal has a level of 0.

11. An optical communication system comprising:

a transmitter circuit configured to generate an optical signal according to a transmitted signal by direct laser modulation and output the optical signal;

a transmission path configured to transmit the optical signal; and

a receiver circuit configured to receive the optical signal and recover a received data corresponding to the transmitted data signal,

wherein the receiver circuit includes;

a receiving part configured to generate a received data signal from the optical signal received from the transmission path;

a data acquisition circuit configured to acquire the received data signal according to a transition edge of a received signal recovery clock; and

a phase adjustment circuit configured to adjust a phase relationship between the transition edge of the received signal recovery clock and the received data signal according to the data value of the received data signal to be acquired by the data acquisition circuit, wherein

the phase adjustment circuit comprises a clock phase adjustment circuit configured to generate an adjustment-completed received signal recovery clock by adjusting a phase of the transition edge of the received signal recovery clock according to the data value of the received data signal to be acquired by the data acquisition circuit,

the data acquisition circuit acquires the received data signal according to the transition edge of the adjustment-completed received signal recovery clock,

the received data signal is a signal received in the form of an optical signal by direct laser modulation, and

the clock phase adjustment signal is configured to make the transition edge of the received signal recovery clock faster when the received data signal has a level of 1 and make the transition edge of the received signal recovery clock slower when the received data signal has a level of 0.