Packet output processing

• US 9,680,742 B2
• Filed: 02/28/2014
• Issued: 06/13/2017
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Snyder, II, Wilson P., Folsom, Brian Robert, Tompkins, Joseph B., Kessler, Richard E., Langevin, Edwin, Jones, Andrew J., Robbins, Ethan F., Mylavarapu, Krupa Sagar O. S., Dorai, Mahesh, Shirali, Nagaraj G., Hallur, Ranjith Kumar V.
• Primary Examiner(s): SWEET, LONNIE V
• Application Number:
  US14/193,895
• Publication Number:
  US 20150249603A1
• Time in Patent Office: 1,201 Days
• CPC Class Codes: H04L 45/566 Routing instructions carried by the data packet, e.g. active networks
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 47/821 Prioritising resource allocation or reservation requests
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Claims

1. A circuit for managing transmittal of packets, the circuit comprising:

a packet descriptor manager (PDM) circuit module configured to generate a metapacket and a descriptor from a command signal, the command signal identifying a packet to be transmitted by the circuit, the metapacket including an entry stating a size of the packet;

a packet scheduling engine (PSE) circuit module configured to determine an order in which to transmit the packet among a plurality of packets, the PSE determining whether to select the packet as a next packet in the order based on a time at which the metapacket is advanced from a modeled endpoint node, the time being a function of the size and a destination across a network of the packet indicated in the metapacket; and

a packet engines and buffering module (PEB) circuit module configured to perform processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor, the PEB causing the processed packet to be transmitted toward the destination.

2. The circuit of claim 1, wherein the PDM further includes a metapacket queue, the PDM being configured to store the metapacket to the metapacket queue.

3. The circuit of claim 2, wherein the PSE is further configured to retrieve at least a portion of the metapacket from the metapacket queue.

4. The circuit of claim 1, wherein the PDM further includes a descriptor queue, the PDM being configured to store the descriptor to the descriptor queue.

5. The circuit of claim 4, wherein the PEB is further configured to retrieve at least a portion of the descriptor from the descriptor queue.

6. The circuit of claim 1, wherein the PSE is further configured to compare a packet transmission rate associated with the destination against at least one of a peak rate and a committed rate associated with the destination, the PSE determining the order based on the comparison.

7. The circuit of claim 6, wherein the PSE is further configured to assign a color to the packet based on the comparison.

8. The circuit of claim 6, wherein the PSE is further configured to compare, for a plurality of nodes in a path between the circuit and the destination, a packet transmission rate associated with the node against at least one of a peak rate and a committed rate associated with the node, the PSE determining the order based on the comparison.

9. The circuit of claim 1, wherein the PSE is further configured to model transmission of the packet through a model of a network topology from the destination to the circuit, the PSE determining the order based on the model transmission.

10. The circuit of claim 9, wherein the PSE is further configured to model a plurality of nodes in the network topology between the destination and the circuit.

11. The circuit of claim 9, wherein the PSE is further configured to determine the order based on arrival of the packet relative to other packets at the circuit in the model transmission.

12. The circuit of claim 11, wherein the PSE is further configured to model transmission of the plurality of packets from a plurality of respective destinations to the circuit, the PSE determining the order based arrival of the packet among the plurality of packets in the model transmission.

13. The circuit of claim 12, wherein the PSE is further configured to model a plurality of nodes in the network topology between the plurality of destinations and the circuit.

14. The circuit of claim 13, wherein the PSE is further configured to assign relative priority to each of the inputs of the model plurality of nodes.

15. The circuit of claim 13, wherein the PSE is further configured to model transmission of the plurality of packets through the model plurality of nodes based on a deficit-weighted round robin calculation.

16. The circuit of claim 1, wherein the PEB is further configured to construct the packet based on pointers in the descriptor, the pointers indicating addresses of a memory storing the packet.

17. The circuit of claim 1, wherein the PEB is further configured to store the processed packet to an output buffer, the PEB causing the packet to be transmitted based on a credit status associated with the buffer.

18. The circuit of claim 1, wherein the metapacket includes an indication of a size of the packet and instructions for ordering the packet.

19. The circuit of claim 1, wherein the descriptor includes 1) pointers indicating addresses of a memory storing the packet and 2) instructions for processing the packet by the PEB.

20. The circuit of claim 1, wherein the command signal further indicates instructions for constructing and processing the packet.

21. The circuit of claim 1, wherein the PEB is further configured to mark the packet with a color indicating compliance with packet traffic rules.

22. The circuit of claim 1, wherein the PEB is further configured to add a timestamp to the packet.

23. The circuit of claim 1, wherein the PEB is further configured to drop a packet based on an indication from the PSE.

24. A method of managing transmittal of packets, the method comprising:

receiving, at a circuit for managing transmittal of packets, a command signal identifying a packet to be processed and transmitted;

generating, at the circuit, a metapacket from the command signal, the metapacket including an entry stating a size of the packet and instructions for ordering the packet;

generating, at the circuit, a descriptor from the command signal, the descriptor including

     1) pointers indicating addresses of a memory storing the packet and

     2) instructions for processing the packet;

determining, at the circuit, whether to select the packet as a next packet in an order in which to transmit the packet among a plurality of packets based on a time at which the metapacket is advanced from a modeled endpoint node, the time being a function of the size and a destination across a network of the packet indicated in the metapacket;

processing, at the circuit, operations on the packet to produce a processed packet based on instructions indicated in the descriptor; and

causing, at the circuit, the processed packet to be transmitted toward the destination.