Wafer level chip scale packaged micro-electro-mechanical-system (MEMS) device and methods of producing thereof
First Claim
1. A packaged micro-electro-mechanical-system (MEMS) device comprising:
- a silicon substrate having a first surface, and a second surface, wherein the second surface is on a side opposite the first surface;
at least one top substrate pad formed on said first surface;
an integrated circuit substrate having at least one bottom substrate pad bonded to the at least one top substrate pad;
at least one recess in the silicon substrate;
at least one other recess in the integrated circuit substrate, wherein the at least one recess in the silicon substrate and the at least one other recess in the integrated circuit substrate define at least one cavity, wherein the at least one cavity is filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of;
1 bar to 10 bar;
1 bar to 5 bar; and
1 bar to 3 bar;
at least one through silicon via (TSV) formed through the silicon substrate, the at least one TSV being connected to the at least one top substrate pad, wherein said at least one TSV comprises a linear passivation layer, a conductive material, and a filling material, wherein the linear passivation layer is disposed on the silicon substrate along sidewalls of the at least one TSV, and the conductive material is disposed on the linear passivation layer in the at least one TSV;
a metal layer formed over the second surface and disposed over the at least one TSV;
at least one electrical bump formed over the metal layer on the second surface of said silicon substrate, wherein each of the at least one electrical bump is in electrical contact with the metal layer, the conductive material in the at least one TSV, and the at least one top substrate pad; and
a substrate passivation layer formed between the metal layer and said silicon substrate.
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Accused Products
Abstract
Packaged MEMS devices are described. One such device includes a substrate having an active surface with an integrated circuit. Two substrate pads are formed on the substrate; one pad is a closed ring pad. The device also includes a cap wafer with two wafer pads. One of these wafer pads is also a closed ring pad. A hermetic seal ring is formed by a first bonding between the two ring pads. The device has a gap between the substrate and the cap wafer. This gap may be filled with a pressurized gas. An electrical connection is formed by a second bonding between one substrate pad and one wafer pad. An electrical contact is disposed over the cap wafer. The device also includes an insulation layer between the electrical contact and the cap wafer. Methods of producing the packaged MEMS devices are also described.
12 Citations
15 Claims
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1. A packaged micro-electro-mechanical-system (MEMS) device comprising:
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a silicon substrate having a first surface, and a second surface, wherein the second surface is on a side opposite the first surface; at least one top substrate pad formed on said first surface; an integrated circuit substrate having at least one bottom substrate pad bonded to the at least one top substrate pad; at least one recess in the silicon substrate; at least one other recess in the integrated circuit substrate, wherein the at least one recess in the silicon substrate and the at least one other recess in the integrated circuit substrate define at least one cavity, wherein the at least one cavity is filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of;
1 bar to 10 bar;
1 bar to 5 bar; and
1 bar to 3 bar;at least one through silicon via (TSV) formed through the silicon substrate, the at least one TSV being connected to the at least one top substrate pad, wherein said at least one TSV comprises a linear passivation layer, a conductive material, and a filling material, wherein the linear passivation layer is disposed on the silicon substrate along sidewalls of the at least one TSV, and the conductive material is disposed on the linear passivation layer in the at least one TSV; a metal layer formed over the second surface and disposed over the at least one TSV; at least one electrical bump formed over the metal layer on the second surface of said silicon substrate, wherein each of the at least one electrical bump is in electrical contact with the metal layer, the conductive material in the at least one TSV, and the at least one top substrate pad; and a substrate passivation layer formed between the metal layer and said silicon substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification