Timing control circuit
First Claim
1. A timing control circuit, comprising:
- a first variable delay circuit configured to receive first data having a first communication speed, and to delay the first data by a variable delay;
a first multiplexer configured to receive an output of the first variable delay circuit, and to convert, based on a reception clock, the first data into second data having a second communication speed different from the first communication speed;
a second replicating variable delay circuit configured to receive third data having the first communication speed, and to delay the third data by another replicating variable delay which substantially replicates the variable delay of the first variable delay circuit according to a transmission clock for a second multiplexer transmitting the first data having the second communication speed to the first variable delay circuit;
a decision circuit configured to compare a phase of the delayed third data output of the replicating second variable delay circuit and a phase of the reception clock; and
a control circuit configured to control the variable delay of the first variable delay circuit and the another replicating variable delay of the second replicating variable delay circuit based on the comparison of the decision circuit.
1 Assignment
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Accused Products
Abstract
A timing control circuit includes a first variable-delay circuit, a multiplexer, a second variable-delay circuit, a decision circuit, and a control circuit. The first variable-delay circuit receives first data having a first communication speed and delays the first data by a variable delay. The multiplexer receives a first variable-delay circuit output and converts, based on a first control signal, the first data into second data having a second communication speed different from the first communication speed. The second variable-delay circuit receives third data having the first communication speed, and delays the third data by another variable-delay corresponding to the variable-delay of the first variable-delay circuit. The decision circuit compares a second variable-delay circuit output phase and a first control signal phase. The control circuit controls the variable-delay of the first variable-delay circuit and the another variable delay of the second variable-delay circuit based on decision circuit comparison.
36 Citations
14 Claims
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1. A timing control circuit, comprising:
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a first variable delay circuit configured to receive first data having a first communication speed, and to delay the first data by a variable delay; a first multiplexer configured to receive an output of the first variable delay circuit, and to convert, based on a reception clock, the first data into second data having a second communication speed different from the first communication speed; a second replicating variable delay circuit configured to receive third data having the first communication speed, and to delay the third data by another replicating variable delay which substantially replicates the variable delay of the first variable delay circuit according to a transmission clock for a second multiplexer transmitting the first data having the second communication speed to the first variable delay circuit; a decision circuit configured to compare a phase of the delayed third data output of the replicating second variable delay circuit and a phase of the reception clock; and a control circuit configured to control the variable delay of the first variable delay circuit and the another replicating variable delay of the second replicating variable delay circuit based on the comparison of the decision circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification