Computing system with non-disruptive fast memory restore mechanism and method of operation thereof
First Claim
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1. A method for operating a computing system comprising:
- monitoring a central interface for a power event, wherein monitoring the central interface includes detecting a power-on sequence during system initialization;
training a high-speed volatile memory during the system initialization to determine a fastest write speed of the high-speed volatile memory by performing a series of write and read operations to and from the high-speed volatile memory at predetermined rates and increasing in write speed;
accessing a non-volatile memory during the power event for pre-shutdown data previously stored on the high-speed volatile memory;
selecting a multiplexer for allowing external access to the high-speed volatile memory;
formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface, wherein formatting the pre-shutdown data includes formatting the pre-shutdown data after detecting the power-on sequence; and
transferring the pre-shutdown data from the non-volatile memory to the high-speed volatile memory after the high-speed volatile memory training is finished, the non-volatile memory accessed through the non-disruptive interface, the high-speed volatile memory accessed through an access controller, and the high-speed volatile memory configured for the fastest write speed.
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Abstract
A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface.
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Citations
18 Claims
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1. A method for operating a computing system comprising:
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monitoring a central interface for a power event, wherein monitoring the central interface includes detecting a power-on sequence during system initialization; training a high-speed volatile memory during the system initialization to determine a fastest write speed of the high-speed volatile memory by performing a series of write and read operations to and from the high-speed volatile memory at predetermined rates and increasing in write speed; accessing a non-volatile memory during the power event for pre-shutdown data previously stored on the high-speed volatile memory; selecting a multiplexer for allowing external access to the high-speed volatile memory; formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface, wherein formatting the pre-shutdown data includes formatting the pre-shutdown data after detecting the power-on sequence; and transferring the pre-shutdown data from the non-volatile memory to the high-speed volatile memory after the high-speed volatile memory training is finished, the non-volatile memory accessed through the non-disruptive interface, the high-speed volatile memory accessed through an access controller, and the high-speed volatile memory configured for the fastest write speed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computing system comprising:
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an event detector coupled to a central interface, with the event detector for monitoring the central interface for a power event, wherein monitoring the central interface includes detecting a power-on sequence during system initialization; a multiplexer, coupled to the central interface, for accessing a high-speed volatile memory through an access controller; an access controller, coupled to the multiplexer, for accessing the high-speed volatile memory; a memory controller, coupled to the multiplexer, for accessing a non-volatile memory during the power event for pre-shutdown data previously stored on the high-speed volatile memory, and the memory controller having; an on-sequence module for selecting the multiplexer to allow external access to the high-speed volatile memory, for training a high-speed volatile memory during the system initialization to determine a fastest write speed of the high-speed volatile memory by performing a series of write and read operations to and from the high-speed volatile memory at predetermined rates and increasing in write speed, and for transferring the pre-shutdown data from the non-volatile memory to the high-speed volatile memory after the high-speed volatile memory training is finished and with the high-speed volatile memory configured for the fastest write speed; and a format module for formatting the pre-shutdown data in the non-volatile memory for access through the non-disruptive interface, wherein formatting the pre-shutdown data includes formatting the pre-shutdown data after detecting the power-on sequence. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification