Computing system with non-disruptive fast memory restore mechanism and method of operation thereof

• US 9,684,520 B2
• Filed: 10/20/2011
• Issued: 06/20/2017
• Est. Priority Date: 10/20/2011
• Status: Active Grant

• Current Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Original Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Inventors: Frey, Robert Tower, Brooks, Joshua Harris
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US13/277,720
• Publication Number:
  US 20130103887A1
• Time in Patent Office: 2,070 Days
• Field of Search: 711162, 711105, 711106, 711154, 711156, 711160, 713 1, 713 2, 713330, 713340
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 9/442 Shutdown

Abstract

A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface.

Claims

1. A method for operating a computing system comprising:

monitoring a central interface for a power event, wherein monitoring the central interface includes detecting a power-on sequence during system initialization;

training a high-speed volatile memory during the system initialization to determine a fastest write speed of the high-speed volatile memory by performing a series of write and read operations to and from the high-speed volatile memory at predetermined rates and increasing in write speed;

accessing a non-volatile memory during the power event for pre-shutdown data previously stored on the high-speed volatile memory;

selecting a multiplexer for allowing external access to the high-speed volatile memory;

formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface, wherein formatting the pre-shutdown data includes formatting the pre-shutdown data after detecting the power-on sequence; and

transferring the pre-shutdown data from the non-volatile memory to the high-speed volatile memory after the high-speed volatile memory training is finished, the non-volatile memory accessed through the non-disruptive interface, the high-speed volatile memory accessed through an access controller, and the high-speed volatile memory configured for the fastest write speed.

2. The method as claimed in claim 1 wherein:

monitoring the central interface includes detecting a power-off sequence; and

formatting the pre-shutdown data includes preserving the speed of the interface between the non-volatile memory and the high-speed volatile memory after detecting the power-off sequence.

3. The method as claimed in claim 1 further comprising enabling simultaneous access to the non-volatile memory through the non-disruptive interface and to the high-speed volatile memory through the central interface.

4. The method as claimed in claim 1 wherein formatting the pre-shutdown data includes formatting the pre-shutdown data for communicating through a serial advanced technology attachment interface or a universal serial bus interface.

5. The method as claimed in claim 1 further comprising:

transferring the pre-shutdown data from the high-speed volatile memory to the non-volatile memory during a power-off sequence; and

wherein;

selecting the multiplexer includes selecting the multiplexer through the central interface; and

formatting the pre-shutdown data includes formatting the pre-shutdown data for access through the non-disruptive interface during the power-on sequence.

6. The method as claimed in claim 5 wherein accessing the high-speed volatile memory includes reading a double data rate random synchronous dynamic random access memory.

7. The method as claimed in claim 5 wherein accessing the non-volatile memory includes accessing a flash memory.

8. The method as claimed in claim 5 wherein accessing the non-volatile memory includes writing the pre-shutdown data to the non-volatile memory during the power-off sequence.

9. The method as claimed in claim 5 wherein accessing the non-volatile memory includes reading the pre-shutdown data from the non-volatile memory during the power-on sequence.

10. A computing system comprising:

an event detector coupled to a central interface, with the event detector for monitoring the central interface for a power event, wherein monitoring the central interface includes detecting a power-on sequence during system initialization;

a multiplexer, coupled to the central interface, for accessing a high-speed volatile memory through an access controller;

an access controller, coupled to the multiplexer, for accessing the high-speed volatile memory;

a memory controller, coupled to the multiplexer, for accessing a non-volatile memory during the power event for pre-shutdown data previously stored on the high-speed volatile memory, and

the memory controller having;

an on-sequence module for selecting the multiplexer to allow external access to the high-speed volatile memory, for training a high-speed volatile memory during the system initialization to determine a fastest write speed of the high-speed volatile memory by performing a series of write and read operations to and from the high-speed volatile memory at predetermined rates and increasing in write speed, and for transferring the pre-shutdown data from the non-volatile memory to the high-speed volatile memory after the high-speed volatile memory training is finished and with the high-speed volatile memory configured for the fastest write speed; and

a format module for formatting the pre-shutdown data in the non-volatile memory for access through the non-disruptive interface, wherein formatting the pre-shutdown data includes formatting the pre-shutdown data after detecting the power-on sequence.

11. The system as claimed in claim 10 wherein:

the event detector is for detecting a power-off sequence; and

the format module is for preserving the speed of the interface between the non-volatile memory and the high-speed volatile memory after detecting the power-off sequence.

12. The system as claimed in claim 10 wherein the memory controller is for enabling simultaneous access to the non-volatile memory through the non-disruptive interface and to the high-speed volatile memory through the central interface.

13. The system as claimed in claim 10 wherein the format module is for formatting the pre-shutdown data for communicating through a serial advanced technology attachment interface or a universal serial bus interface.

14. The system as claimed in claim 10 further comprising:

an off-sequence module, coupled to the multiplexer, for transferring the pre-shutdown data from the high-speed volatile memory to the non-volatile memory during a power-off sequence; and

wherein;

the format module is for formatting the pre-shutdown data for access through the non-disruptive interface during the power-on sequence.

15. The system as claimed in claim 14 wherein the high-speed volatile memory is a double pre-shutdown data rate random synchronous dynamic random access memory.

16. The system as claimed in claim 14 wherein the non-volatile memory is a flash memory.

17. The system as claimed in claim 14 wherein the off-sequence module is for writing the pre-shutdown data to the non-volatile memory during the power-off sequence.

18. The system as claimed in claim 14 wherein the on-sequence module is for reading the pre-shutdown data from the non-volatile memory during the power-on sequence.