Data storage device and flash memory control method

• US 9,684,568 B2
• Filed: 11/06/2014
• Issued: 06/20/2017
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Liang, Chia-Chi, Huang, Chang-Chieh, Lee, Jie-Hao
• Primary Examiner(s): PEREZ-VELEZ, ROCIO DEL MAR
• Application Number:
  US14/534,633
• Publication Number:
  US 20150186263A1
• Time in Patent Office: 957 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer.

Claims

1. A data storage device, comprising:

a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein;

the microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory, allocates the blocks of the flash memory to provide a system block, and records a link table indicator in the system block to indicate a position of the link table;

the link table indicates positions of the plurality of logical-to-physical address mapping tables, each entry in the link table corresponds to one logical-to-physical address mapping table; and

wherein the microcontroller erases user data of logical addresses corresponding to N logical-to-physical address mapping tables by downloading the link table from the flash memory to the random access memory, invalidating N entries corresponding to the N logical-to-physical address mapping tables in the link table on the random access memory, uploading the link table with the N entries of invalid data back to the flash memory, and updating the system block with an updated link table indicator, where N is an integer.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller downloads the link table from the flash memory to the random access memory in accordance with the link table indicator recorded in the system block.

3. The data storage device as claimed in claim 1, wherein:

the link table indicator indicates the position of the link table by a block number and a page number.

4. The data storage device as claimed in claim 1, wherein:

each entry in the link table stores a block number and a page number that indicate the position of the logical-to-physical address mapping table corresponding thereto.

5. A flash memory control method, comprising:

maintaining a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory, wherein the flash memory provides a storage space divided into a plurality of blocks with each block comprising a plurality of pages, the link table indicates positions of the plurality of logical-to-physical address mapping tables, each entry in the link table corresponds to one logical-to-physical address mapping table,

allocating the blocks of the flash memory to provide a system block;

recording a link table indicator in the system block to indicate a position of the link table;

erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables by downloading the link table from the flash memory to a random access memory, invalidating N entries corresponding to the N logical-to-physical address mapping tables in the link table on the random access memory, uploading the link table with the N entries of invalid data back to the flash memory, and updating the system block with an updated link table indicator, where N is an integer.

6. The flash memory control method as claimed in claim 5, wherein:

the link table is downloaded from the flash memory to the random access memory in accordance with the link table indicator recorded in the system block.

7. The flash memory control method as claimed in claim 5, wherein:

the link table indicator indicates the position of the link table by a block number and a page number.

8. The flash memory control method as claimed in claim 5, wherein:

each entry in the link table stores a block number and a page number that indicate the position of the logical-to-physical address mapping table corresponding thereto.