Receive clock calibration for a serial bus
First Claim
1. A method operational on a master device, comprising:
- providing a clock signal on a serial clock line (SCL line) of a serial bus, wherein the clock signal controls data transmissions on a serial data line (SDA line) of the serial bus;
generating a receive clock from transitions on the SCL line when a slave device is transmitting data on the SDA line;
calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal;
providing a modified receive clock by adding the delay to the receive clock; and
receiving data from the SDA line using the modified receive clock,wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line.
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Accused Products
Abstract
Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock.
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Citations
23 Claims
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1. A method operational on a master device, comprising:
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providing a clock signal on a serial clock line (SCL line) of a serial bus, wherein the clock signal controls data transmissions on a serial data line (SDA line) of the serial bus; generating a receive clock from transitions on the SCL line when a slave device is transmitting data on the SDA line; calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal; providing a modified receive clock by adding the delay to the receive clock; and receiving data from the SDA line using the modified receive clock, wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus configured to function as a master device when coupled to a serial data link, comprising:
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a transmitting circuit configured to transmit a first clock signal on a serial clock line (SCL line) of the serial data link, wherein the first clock signal controls data transmissions on a serial data line (SDA line) of the serial data link; a clock generation circuit configured to generate a second clock from transitions of the clock signal when a slave device is transmitting data on the SDA line; calibration logic configured to calibrate a delay based on a duration of time measured between an edge of the first clock signal and at least one transition produced on the SDA line by a slave device in response to the edge of the first clock signal, and provide a third clock by adding the delay to the second clock; and a receiving circuit configured to receive data from the SDA line using the third clock, wherein the first clock signal controls double data rate transmissions on the SDA line. - View Dependent Claims (9, 10, 11, 12)
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13. An apparatus configured to function as a master device when coupled to a serial data link, comprising:
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means for providing a clock signal on a serial clock line (SCL line) of a serial bus, wherein the clock signal controls data transmissions on a serial data line (SDA line) of the serial bus; means for generating a receive clock from transitions on the SCL line when a slave device is transmitting data on the SDA line; means for calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal; means for providing a modified receive clock by adding the delay to the receive clock; and means for receiving data from the SDA line using the modified receive clock, wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method operational on a slave device, comprising:
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receiving a clock signal from a serial clock line (SCL line) of a serial bus, wherein the clock signal is generated by a master device and controls data transmissions on a serial data line (SDA line) of the serial bus; generating a receive clock from transitions on the SCL line when a peer slave device is transmitting data on the SDA line; calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal; providing a modified receive clock by adding the delay to the receive clock; and receiving data from the SDA line using the modified receive clock, wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line. - View Dependent Claims (21, 22, 23)
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Specification