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Receive clock calibration for a serial bus

  • US 9,684,624 B2
  • Filed: 02/06/2015
  • Issued: 06/20/2017
  • Est. Priority Date: 01/14/2014
  • Status: Active Grant
First Claim
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1. A method operational on a master device, comprising:

  • providing a clock signal on a serial clock line (SCL line) of a serial bus, wherein the clock signal controls data transmissions on a serial data line (SDA line) of the serial bus;

    generating a receive clock from transitions on the SCL line when a slave device is transmitting data on the SDA line;

    calibrating a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal;

    providing a modified receive clock by adding the delay to the receive clock; and

    receiving data from the SDA line using the modified receive clock,wherein the clock signal provided on the SCL line controls double data rate transmissions on the SDA line.

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