Systems for synchrophasor data managment

• US 9,684,700 B2
• Filed: 02/29/2016
• Issued: 06/20/2017
• Est. Priority Date: 12/09/2012
• Status: Active Grant

• Current Assignee: GE Infrastructure Technology, LLC (General Electric Company)
• Original Assignee: General Electric Company
• Inventors: Aguirre, Oscar Lopez, Argandona, Rodrigo Gutierrez, Rodrigues, Jason Antonio, Adamiak, Mark Gerard, Kanabar, Mitalkumar Gulabrai
• Primary Examiner(s): To, Baoquoc N
• Application Number:
  US15/056,867
• Publication Number:
  US 20160253396A1
• Time in Patent Office: 477 Days
• Field of Search: 707803, 707808
• CPC Class Codes: G01R 19/2513 Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
• CPC Class Codes: G01R 21/00 Arrangements for measuring electric power or power factor G01R7/12 takes precedence
• CPC Class Codes: G01R 23/02 Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
• CPC Class Codes: G06F 16/2228 Indexing structures
• CPC Class Codes: G06F 16/258 Data format conversion from or to a database
• CPC Class Codes: H04Q 9/00 Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
• CPC Class Codes: Y02E 40/70 Smart grids as climate change mitigation technology in the energy generation sector
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 10/00 Systems supporting electrical power generation, transmission or distribution
• CPC Class Codes: Y04S 10/22 Flexible AC transmission systems [FACTS] or power factor or reactive power compensating or correcting units

Abstract

A system includes a Synchrophasor Data Management System (SDMS), in which the SDMS includes a Synchrophasor Processor System (SPS). The SPS includes a Phasor Data Concentrator (PDC) configured to receive a first plurality of inputs from a first Phasor Measurement Unit (PMU), transform at least one of the first plurality of inputs into a first time aligned output by time aligning the at least one of the first plurality of inputs. The SPS further includes a virtual PMU configured to aggregate the first time aligned output into a PMU dataset, in which the SPS is configured to transmit the PMU dataset to a second PMU, an external PDC, a super PDC, or a combination thereof.

Claims

1. A system comprising:

a processor;

a memory including instructions that, when executed by the processor, cause the processor to perform operations comprising;

receiving a plurality of phasor measurement unit (PMU) signals by executing a Phasor Data Concentrator (PDC) module;

converting one of the PMU signals into a first data structure having an agnostic format by executing an input protocol handler module;

converting the first data structure into a synchrophasor-related signal by executing an output protocol handler module;

converting data associated with another one of the received PMU signals into predetermined fields of a second data structure by executing a pseudo-PMU module; and

combining, by executing the pseudo-PMU module, the second data structure with the synchrophasor-related signal to create an output signal.

2. The system of claim 1, wherein the system is implemented on a single circuit board in a computer system.

3. The system of claim 1, wherein the operations further comprise transmitting the output signal to a device selected from the group consisting of a PDC and a PMU.

4. The system of claim 1, wherein the receiving includes receiving PMU signals having different data rates.

5. The system of claim 1, wherein the receiving includes receiving PMUS signals having the same data rates.

6. The system of claim 1, wherein the data associated with the other one of the received PMU signal includes alert data, diagnostic data, or a combination thereof.

7. The system of claim 1, further comprising one of (i) an application system configured to process phasor data and (ii) a logging system configured to store data.

8. The system of claim 1, wherein the system is implemented on a plurality of circuit boards in a computer system.

9. The system of claim 8, further comprising a chassis having a redundant power supply and a data bus.

10. The system of claim 9, wherein the circuit boards are each communicatively coupled to the data bus.

11. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform operations comprising:

receiving a plurality of phasor measurement unit (PMU) signals;

converting one of the PMU signals into a first data structure having an agnostic format;

converting the first data structure into a synchrophasor-related signal;

converting data associated with another one of the received PMU signals into predetermined fields of a second data structure; and

combining the second data structure with the synchrophasor-related signal to create an output signal.

12. The non-transitory computer-readable medium of claim 11, wherein the operations further comprise transmitting the output signal to a device selected from the group consisting of a PDC and a PMU.

13. The non-transitory computer-readable medium of claim 11, wherein the receiving includes receiving PMU signals having different data rates.

14. The non-transitory computer-readable medium of claim 11, wherein the receiving includes receiving PMU signals having the same data rate.

15. The non-transitory computer-readable medium of claim 11, wherein the data associated with the other one of the received PMU signal includes alert data, diagnostic data, or a combination thereof.

16. The non-transitory computer-readable medium of claim 11, wherein the one of the PMU signals is in a first format and the synchrophasor-related signal is in a second format.

17. The non-transitory computer-readable medium of claim 16, wherein the first format and the second format are the same.

18. The non-transitory computer-readable medium of claim 16, wherein the first format and the second format are different.

19. The non-transitory computer-readable medium of claim 16, wherein the first format is based on IEEE C37.118X.

20. The non-transitory computer-readable medium of claim 16, wherein the second format is based on IEC 61850-90-5.