Isolated debugging in an FPGA based emulation environment

• US 9,684,743 B2
• Filed: 06/19/2015
• Issued: 06/20/2017
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Larzul, Ludovic Marc
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/745,239
• Publication Number:
  US 20160371407A1
• Time in Patent Office: 732 Days
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has been mapped. Additionally, mapped to each FPGA is trace and injection logic that traces signals exchanged by the FPGA with other FPGAs during emulation of the DUT. After the emulation of the DUT is complete, if a user wishes to debug a component of the DUT, the FPGAs that are configured to emulate the component are identified. For each identified FPGA, the trace and injection logic injects previously traced signals into the logic of the FPGA in order to reemulate the component. The host system generates waveforms for the user that include signals traced during the reemulation of the component.

Claims

1. A non-transitory computer readable storage medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to:

receive, from an emulator, a plurality of interface signals, the emulator including a plurality of field-programmable gate arrays (FPGAs), the plurality of interface signals generated by tracing interfaces from the plurality of FPGAs during a first emulation of a design under test (DUT);

after the first emulation of the DUT, transmit to the emulator instructions to run a second emulation of at least a portion of the DUT using a subset of FPGAs from the plurality of FPGAs and one or more interface signals from the plurality of interface signals; and

receive from the emulator traced signals traced during the second emulation by running of the subset of FPGAs based on the one or more interface signals from the plurality of interface signals.

2. The non-transitory computer readable medium of claim 1, further comprising instructions when executed by the one or more processors further cause the one or more processors to:

store the plurality of interface signals;

receive a request to emulate an element of the DUT;

identify, from the plurality of FPGAs, the subset of FPGAs configured to emulate the element;

identify, from the plurality of stored interface signals, the one or more interface signals traced by the subset of FPGAs during the first emulation of the DUT; and

transmit the identified interface signals to the emulator for running the subset of FPGAs during the second emulation.

3. The non-transitory computer readable medium of claim 2, wherein the request to emulate includes a time period associated with the first emulation of the DUT and the identified interface signals are associated with the time period.

4. The non-transitory computer readable medium of claim 2, wherein the element is a component of the DUT.

5. The non-transitory computer readable medium of claim 2, wherein the element is a signal of the DUT.

6. The non-transitory computer readable medium of claim 1, wherein an additional subset from the plurality of FPGAs are not run when the subset of FPGAs are run during the second emulation.

7. The non-transitory computer readable medium of claim 1, wherein the plurality of interface signals comprise signals exchanged between FPGAs from the plurality of FPGAs.

8. The non-transitory computer readable medium of claim 1, wherein logic of the DUT is mapped to each FPGA from the subset of FPGAs and the logic of each FPGA receives one or more interface signals as inputs during the running of the subset of FPGAs in the second emulation.

9. The non-transitory computer readable medium of claim 1, wherein an FPGA from the subset of FPGAs is configured to emulate logic of the DUT and the non-transitory computer readable medium further comprising instructions when executed by the one or more processors further cause the one or more processors to:

transmit instructions to the emulator to configure additional FPGAs of the emulator to emulate the logic; and

transmitting instructions to the emulator for each additional FPGA to run using a different time window of one or more interface signals from the plurality of signals.

10. A non-transitory computer readable storage medium storing instructions that configure an emulator to:

trace interface signals exchanged between a first FPGA and one or more additional FPGAs during a first emulation of a design under test (DUT), the first FPGA configured to emulate an element of the DUT; and

after the first emulation of the DUT, run the first FPGA during a second emulation using the traced interface signals based on a request to emulate the element.

11. The non-transitory computer readable medium of claim 10, further comprising instructions when executed by the one or more processors further cause the one or more processors to:

transmit the interface signals to a host system; and

receive the interface signals from the host system for the second emulation.

12. The non-transitory computer readable medium of claim 10, wherein the additional FPGAs are not run during the second emulation.

13. The non-transitory computer readable medium of claim 10, wherein the first FPGA includes logic configured to emulate the element and the logic receives the interface signals as inputs during the second emulation.

14. The non-transitory computer readable medium of claim 10, further comprising instructions when executed by the one or more processors further cause the one or more processors to:

trace additional signals during the second emulation; and

transmit the additional signals to the host system.

15. A method comprising:

receiving, from an emulator, a plurality of interface signals, the emulator including a plurality of reconfigurable logic blocks, the plurality of interface signals generated by tracing interfaces from the plurality of reconfigurable logic blocks during a first emulation of a design under test (DUT);

after the first emulation of the DUT, requesting that during a second emulation of at least a portion of the DUT the emulator run a subset of blocks from the plurality of reconfigurable logic blocks based on one or more interface signals from the plurality of interface signals; and

receiving from the emulator traced signals traced during the second emulation by running the subset of blocks based on the one or more interface signals from the plurality of interface signals.

16. The method of claim 15, further comprising:

storing the plurality of interface signals;

receiving a request to emulate an element of the DUT;

identifying, from the plurality of reconfigurable logic blocks, the subset of blocks configured to emulate the element;

identifying, from the plurality of stored interface signals, the one or more interface signals traced by the subset of blocks during the first emulation of the DUT; and

transmitting the identified interface signals to the emulator for running the subset of blocks during the second emulation.

17. The method of claim 16, wherein the request to emulate includes a time period associated with the emulation of the DUT and the identified interface signals are associated with the time period.

18. The method of claim 15, wherein an additional subset from the plurality of reconfigurable logic blocks are not run when the subset of blocks are run during the second emulation.

19. The method of claim 15, wherein the plurality of interface signals comprise signals exchanged between blocks from the plurality of reconfigurable logic blocks.

20. A method comprising:

tracing interface signals exchanged between a first reconfigurable logic block and one or more additional reconfigurable logic blocks during a first emulation of a design under test (DUT), the first block configured to emulate an element of the DUT; and

after the first emulation of the DUT, running the first block during a second emulation using the traced interface signals based on a request to emulate the element.