Frequency selective logarithmic amplifier with intrinsic frequency demodulation capability

• US 9,684,807 B2
• Filed: 03/14/2014
• Issued: 06/20/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: DockOn AG
• Original Assignee: DockOn AG
• Inventors: Brown, Forrest, Rada, Patrick, Dupuy, Alexandre
• Primary Examiner(s): Urban, Edward
• Assistant Examiner(s): HU, RUI MENG
• Application Number:
  US14/213,972
• Publication Number:
  US 20140273898A1
• Time in Patent Office: 1,194 Days
• Field of Search: 455334-3436, 455215, 455254
• CPC Class Codes: G06G 7/24 for evaluating logarithmic or exponential functions, e.g. hyperbolic functions for multiplication, division or for evaluating powers or roots using logarithmic functions; gamma correction in television systems H04N5/20, H04N9/69
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03D 11/04 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 11/08 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 2200/006 Signal sampling
• CPC Class Codes: H03D 3/00 Demodulation of angle-, frequency- or phase- modulated oscillations H03D5/00, H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers

Abstract

A regenerative selective logarithmic detector amplifier (LDA) can have integrated FM demodulation capabilities. It can receive a wired or wireless FM modulated signal and amplify or demodulate it with high sensitivity, high skirt ratio and minimized noise when compared to the prior art. When used in conjunction with other circuits such as a PLL or mixer, it can improve interference rejection and frequency selectivity and be locked on a precise channel in frequency and phase. The LDA produces intermittent oscillations that are self-quenched when reaching a given threshold. It also embeds the circuitry to perform direct FM discrimination. FM demodulation process is completed by a simple analog or digital frequency to voltage converter. This plus the fact that the instantaneous regeneration gain is low-medium permit to detect signals of small amplitudes buried in the noise.

Claims

1. A system for use in a receive chain of a communication device, the system comprising:

an amplifying circuit configured to receive an input signal and to generate an oscillation based on the input signal;

one or more quadripole resonant circuits configured to establish a frequency pass band transfer response with a substantially zero phase region, the one or more quadripole resonant circuits comprising a parallel resonant circuit and a series resonant circuit forming a four terminal network, the one or more quadripole resonant circuits coupled to the amplifying circuit and configured to establish a frequency of operation of the system;

a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold so as to periodically clamp and restart the oscillation to generate a series of voltage spikes, wherein an instantaneous frequency of the voltage spikes carries frequency modulation (FM) and amplitude modulation (AM) modulation information of the input signal and is output as a first output signal, and wherein the first output signal has a different frequency than the input signal;

a first low pass filter circuit coupled between the amplifier circuit and the sampling circuit to isolate the first output signal from the input signal and the oscillation generated by the amplifier; and

a second low pass filter circuit coupled to the one or more quadripole resonant circuits, the second low pass filter circuit configured to generate a second output signal.

2. The system of claim 1, wherein the first low pass filter circuit and the sampling circuit comprise a circuit including a diode.

3. The system of claim 1, wherein the first low pass filter circuit and the sampling circuit comprise a circuit including an inductor.

4. The system of claim 1, wherein the system further comprises:

a frequency to voltage circuit configured to receive the voltage spikes and demodulate the FM and AM modulation information by bringing the FM and AM modulation information to a baseband frequency.

5. The system of claim 1, wherein the output signal is output by one or more of an active node of the sampling circuit, a bias or base of the amplifier, an output of the amplifier, or an active node of the quadripole.

6. The system of claim 1, wherein the sampling circuit is configured to demodulate frequency modulation intrinsically.

7. The system of claim 1, wherein the system is configured to demodulate one or both of the FM and AM modulation information regardless of a signal strength of the input signal.

8. The system of claim 7, wherein the demodulation one or both of the FM and AM modulation provides a gain of additional detection sensitivity.

9. The system of claim 1, wherein the system is configured to demodulate one or both of the FM and AM modulation information regardless of a signal strength of the input signal.

10. The system of claim 1, wherein the system is configured to regenerate the input signal from a noise floor based on an intrinsic low gain and structure to provide a high signal sensitivity.

11. The system of claim 1, wherein the input signal comprises an AM input and the output signal comprises a frequency output.

12. The system of claim 1, wherein the system is configured to regenerate the input signal from a noise floor based on an intrinsic low gain and structure to provide a high signal sensitivity.

13. The system of claim 1, wherein the system provides a skirt ratio with a predetermined level of selectivity.

14. The system of claim 1, wherein the system is configured to convert the output signal from a repetition frequency output to a voltage output using one or more of a frequency to voltage converter or an analog detector.

15. The system of claim 1, wherein the system is configured to convert the output signal from a repetition frequency output to a digital voltage by shaping the repetition frequency output to digital pulses and performing at least one of the following:

performing an instant frequency measurement followed by performing a digital scaling function to obtain the digital voltage output;

or

measuring a period followed by performing an inverter function and digital scaling function to obtain the digital voltage output.

16. The system of claim 15, wherein periods of time between digital pulses of the digital voltage output are counted using a clock at a particular rate.

17. The system of claim 16, where a clock of period substantially 2^N time smaller than the minimum period of time to measure from the digital voltage output is used to provide a digital voltage output with N bits of binary accuracy.

18. The system of claim 1, wherein the system is configured to provide a gain in a range from about 1.001 to about 3 in order to permit regeneration of weak signal from a noise floor.

19. The system of claim 1, wherein the one or more quadripole resonant circuits comprise at least one of an LC circuit, a SAW, a BAW, a line of transmission of given impedance, a line of transmission of given length, or a line of transmission with stubs.

20. The system of claim 1, wherein the system is configured to receive an input bias.

21. The system of claim 20, wherein the input bias comprises one or more of a temperature compensated current source or a temperature compensated voltage source.

22. The system of claim 20, wherein the input bias comprises one or more of a current source or a voltage source.

23. The system of claim 1, wherein the an amplifying circuit comprises one or more of a transistor, an amplifier, a diode, a field-effect transistor (FET), a metal-oxide-semiconductor (MOS), a dual gate amplifier, a GaN amplifier, a Si amplifier, or a silicon complementary metal-oxide-semiconductor (SiCMOS).

24. A system for use in a receive chain of a communication device, the system comprising:

an amplifying circuit configured to receive an input signal and to generate an oscillation based on the input signal;

one or more quadripole resonant circuits configured to establish a frequency pass band transfer response with a substantially zero phase region, the one or more quadripole resonant circuits comprising a parallel resonant circuit and a series resonant circuit forming a four terminal network, the one or more quadripole resonant circuits coupled to the amplifying circuit and configured to establish a frequency of operation of the system;

a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold so as to periodically clamp and restart the oscillation to generate a series of voltage spikes, where an instantaneous frequency of the voltage spikes carries FM and AM modulation information of the input signal and is output as a first output signal, wherein the first output signal has a different frequency than the input signal;

a first low pass filter circuit coupled between the amplifier circuit and the sampling circuit to isolate the first output signal from the input signal and the oscillation generated by the amplifier;

a matching circuit configured to receive at least one of the input signal or the output signal and to improve matching and coupling of one or more of the input signal or the output signal;

an isolation circuit between the input signal and the matching circuit, the isolation circuit configured to reduce leakage of backward energy; and

a second low pass filter circuit coupled to the one or more quadripole resonant circuits, the second low pass filter circuit configured to generate a second output signal.

25. The system of claim 24, wherein the isolation circuit comprises a passive circuit having one or more of a circulator, a splitter, a coupler, and an attenuator.

26. The system of claim 24, wherein the isolation circuit comprises an active circuit having one or more of a low noise amplifier (LNA), and an amplifier.

27. A logarithmic detector amplifier for use in a receive chain of a communication device, the logarithmic detector amplifier comprising:

an FM receiver configured to receive an FM input signal;

an amplifier configured to receive an input signal and to generate an oscillation based on the FM input signal;

at least one quadripole coupled to the amplifier, the at least one quadripole having a parallel resonance circuit and a series resonance circuit, the one or more quadripole resonant circuits comprising a parallel resonant circuit and a series resonant circuit forming a four terminal network, the at least one quadripole configured as a bandpass filter to filter the FM input signal and to cause the amplifier to resonate at a target frequency;

a sampling circuit coupled to the amplifier and configured to terminate the oscillation based on a predetermined threshold so as to periodically clamp and restart the oscillation to generate a series of voltage spikes, wherein an instantaneous frequency of the voltage spikes carries FM modulation information of the FM input signal and is output as a first FM output signal; and

a low pass filter circuit coupled to the one or more quadripole resonant circuits and configured to generate a second output signal,

wherein the target frequency is variable and based on at least one parameter of the logarithmic detector amplifier.

28. The logarithmic detector amplifier of claim 27, wherein the at least one parameter of the logarithmic detector amplifier comprises a capacitance of the at least one quadripole.

29. The logarithmic detector amplifier of claim 28, wherein the target frequency is varied by varying the capacitance of the at least one quadripole.

30. The logarithmic detector amplifier of claim 27, wherein the target frequency is varied by varying a capacitance of the parallel resonance circuit of the at least one quadripole.

31. The logarithmic detector amplifier of claim 30, wherein the parallel resonance circuit of the at least one quadripole has either a variable capacitance or an adjustable capacitance, and wherein the capacitance of the parallel resonance circuit of the at least one quadripole can be varied using either an analog controller or a digital controller.

32. The logarithmic detector amplifier of claim 31, wherein the capacitance of the parallel resonance circuit of the at least one quadripole can be varied using a digital controller, and wherein the digital controller comprises a microcontroller, a field programmable gate array (FPGA), or a logic circuit.

33. The logarithmic detector amplifier of claim 30, wherein the capacitance of the parallel resonance circuit of the at least one quadripole can be varied using an analog controller, and wherein the analog controller comprises on or more of a variable cap button, a potentiometer, or a microcontroller with a digital to analog controller.

34. The logarithmic detector amplifier of claim 27, wherein the output repetition frequency is varied by varying the predetermined threshold level of the sampling circuit, said threshold level can be varied by changing a value of resistor or capacitance.

35. The logarithmic detector amplifier of claim 27, wherein target frequency is varied by varying a bias of the amplifier.

36. The logarithmic detector amplifier of claim 27, wherein target frequency is variable within a range from about 88 MHz to about 108 MHz.

37. The logarithmic detector amplifier of claim 27, wherein the FM input signal is a digital FM modulation RF signal, and wherein the digital FM modulation RF signal comprises one or more of a frequency-shift keying (FSK) signal, a Gaussian frequency-shift keying (GFSK) signal, an n-FSK signal, a Gaussian n-FSK signal, a minimum-shift keying (MSK) signal, or a Gaussian minimum shift keying (GMSK) signal, a Gaussian filtering, a n-ary FSK signal, digital modulation.

38. The logarithmic detector amplifier of claim 37, wherein the target frequency comprises at least one of about 1 GHz, about 168 MHz, about 433 MHz, about 868 MHz, and about 902 MHz.

39. The logarithmic detector amplifier of claim 27, further comprising:

a phase lock loop (PLL) in a closed loop configuration and configured to compare the oscillation to a reference phase or a reference frequency, and wherein the PLL is configured to change the target frequency within a range of values.

40. The logarithmic detector amplifier of claim 39, wherein the change of the target frequency by the PLL can be done to precisely select a particular channel, to correct drift associated with temperature, or to adjust for fix tolerances.

41. The logarithmic detector amplifier of claim 39, wherein the PLL is configured to change the target frequency by changing a parameter of the PLL, and wherein the parameter of the PLL comprises at least one of a divider M or a reference divider N or a reference frequency.