Electronic device using group III nitride semiconductor and its fabrication method and an epitaxial multi-layer wafer for making it

• US 9,685,327 B2
• Filed: 08/14/2014
• Issued: 06/20/2017
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Seoul Semiconductor Co., Ltd.
• Original Assignee: Seoul Semiconductor Co., Ltd., SixPoint Materials, Inc.
• Inventors: Hashimoto, Tadao
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US14/460,065
• Publication Number:
  US 20160293415A1
• Time in Patent Office: 1,041 Days
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02623 Liquid deposition
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8122 : Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10⁵ cm⁻², combined with a high-purity active layer of Ga_1-x-yAl_xIn_yN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

Claims

1. A method of making a multi-layer wafer comprising

(a) epitaxially depositing from vapor phase an active layer of Ga_1-x2-y2Al_x2In_y2N (0≦

x2≦

1, 0≦

y2≦

1) at a first side of a substrate of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) and epitaxially depositing-a transition layer, wherein the transition layer comprises Ga_1-x3-y3Al_x3In_y3N (0≦

x3≦

1, 0≦

y3≦

1) and wherein the transition layer resides between the first side of the substrate and the active layer,

(b) wherein said substrate was formed by an ammonothermal method and said substrate has a second side opposite to the first side,

(c) wherein the active layer and the transition layer are deposited to a combined thickness suitable to form an electronic device on the multi-layer wafer, said combined thickness being greater than a depth of a depletion region which is formed in the active layer after fabricating the electronic device with a first electrode on a top surface of the active layer and a second electrode on the second side of the substrate,

(d) wherein the substrate has an oxygen concentration or an electron concentration greater than 10¹⁸ cm<sup>−

3</sup> and

(e) wherein said vapor phase has a sufficiently low concentration of oxygen or concentration of electrons to provide an oxygen concentration in the active layer of less than 10¹⁸ cm<sup>−

3</sup>.

2. A method according to claim 1 wherein the vapor phase has a sufficiently low concentration of oxygen to provide an oxygen concentration in the active layer of less than 10¹⁶ cm⁻

3.

3. A method according to claim 1 wherein the active layer has a sufficiently low concentration of an electron donor to provide an electron concentration in the active layer of less than 10¹⁶ cm⁻

3.

4. A method according to claim 1 wherein the active layer has a sufficiently low concentration of sodium that the active layer contains at least 100 times less sodium than the substrate, and the substrate contains sodium at a concentration greater than 10¹⁶ cm⁻

3.

5. A method according to claim 4 wherein x1=x2=x3=0 and y1=y2=y3=0.

6. A method according to claim 1 wherein the active layer is deposited to a thickness of at least about 5 microns.

7. A method according to claim 1 which comprises varying a concentration of a reactant and/or deposition conditions so that a first face of the transition layer matches a crystal lattice of the substrate during the depositing and a second, opposite face of the transition layer matches a crystal lattice of the active layer upon completion of depositing the transition layer.

8. A method according to claim 1 wherein the active layer is deposited to a thickness such that the depletion zone extends into a portion of the transition layer.

9. A method according to claim 8 wherein the depletion zone ends before reaching cracks in the transition layer.

10. A method according to claim 1 wherein the transition layer cracks during said depositing, and wherein the method further comprises depositing an additional amount of the transition layer to bury the transition layer cracks so that the second surface of the transition layer has no cracks.

11. A method according to claim 10 wherein the active layer has a sufficiently low concentration of sodium that the active layer contains at least 100 times less sodium than the substrate, and the substrate contains sodium at a concentration greater than 10¹⁶ cm⁻

3.

12. A method according to claim 10 wherein the active layer is deposited to a thickness such that the depletion zone extends into a portion of the transition layer.

13. A method according to claim 12 wherein the depletion zone ends before reaching cracks in the transition layer.

14. A method according to claim 1 wherein the transition layer is doped with an impurity which prevents diffusion of impurities contained in the substrate.

15. A method according to claim 1 and further comprising depositing a current blocking layer between the group III nitride substrate and the active layer.

16. A method according to claim 1 wherein said first side of the substrate is miscut more than 0.1 degree and less than 5 degree to a c plane.

17. A method according to claim 1 and further comprising providing said electrodes.

18. A method according to claim 1 wherein x1=x2=x3=0 and y1=y2=y3=0.