Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

• US 9,685,328 B2
• Filed: 02/19/2016
• Issued: 06/20/2017
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reznicek, Alexander
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/047,838
• Publication Number:
  US 20160322221A1
• Time in Patent Office: 487 Days
• Field of Search: 257190, 438479
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

Claims

1. A structure, comprising:

a substrate having a top surface;

a first semiconductor layer disposed on the top surface of the substrate, the first semiconductor layer having a first unit cell geometry and comprising implanted ions;

a layer comprised of a metal-containing oxide disposed on the first semiconductor layer;

a second semiconductor layer disposed on the layer comprised of the metal-containing oxide, the second semiconductor layer having the first unit cell geometry;

a third semiconductor layer disposed on a top surface of the second semiconductor layer;

where the layer of metal-containing oxide has a second unit cell geometry that differs from the first unit cell geometry to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer and from the second semiconductor layer into the third semiconductor layer, where the misfit dislocations originate from nucleation centers formed by the implanted ions in the first semiconductor layer;

where the second semiconductor layer is comprised of Si_1-xGe_x, and where the third semiconductor layer is comprised of a layer of strained silicon disposed on the top surface of the second semiconductor layer.

2. The structure of claim 1, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of a rare earth metal.

3. The structure of claim 1, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of at least one of cerium oxide (CeO₂), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), gadolinium oxide (Gd₂O₃), europium oxide (Eu₂O₃), terbium oxide (Tb₂O₃), a material ABO₃, where ‘

A’ and

‘

B’

may be any rare earth metal including lanthanum scandium oxide (LaScO₃) and lanthanum yttrium oxide (La_xY_1-x)₂O₃, samarium yttrium oxide (Sm_xY_1-x)₂O₃, lanthanum gadolinium oxide (La_xGd_1-x)₂O₃ and gadolinium europium oxide (Gd_xEu_1-x)₂O₃.

4. The structure of claim 1, where the first semiconductor layer is a strain relaxed layer comprised of Si_1-xGe_x.

5. The structure of claim 1, where the first unit cell geometry exhibits a diamond lattice crystal structure, and where the second unit cell geometry exhibits a cubic lattice crystal structure.

6. The structure of claim 1, where the layer comprised of the metal-containing oxide has a thickness in a range of about 10 nm to about 100 nm, or a thickness in a range of about 20 nm to about 50 nm, or a thickness of about 30 nm.

7. The structure of claim 1, where the first semiconductor layer is comprised of Si_1-xGe_x, and where the third semiconductor layer is comprised of a layer of Si_1-xGe_x disposed on the top surface of the second semiconductor layer, where the value of x in the third semiconductor layer that is comprised of Si_1-xGe_x is greater than the value of x in the first semiconductor layer.

8. The structure of claim 1, embodied as an intermediate structure during fabrication of an integrated circuit.

9. A structure, comprising:

a Silicon substrate having a top surface;

a first Si_1-xGe_x semiconductor layer disposed on the top surface of the Si substrate, the first Si_1-xGe_x semiconductor layer being a strained Si_1-xGe_x semiconductor layer that has a diamond lattice crystal structure, the first Si_1-xGe_x semiconductor layer comprising an implanted material;

a compound epitaxial oxide layer comprised of (La_yY_1-y)₂O₃, where y is about 0.3, disposed on a top surface of the first Si_1-xGe_x semiconductor layer, the compound epitaxial oxide layer having a cubic lattice crystal structure;

a second Si_1-xGe_x semiconductor layer disposed on a top surface of the compound epitaxial oxide layer, the second Si_1-xGe_x semiconductor layer having the diamond lattice crystal structure;

a third semiconductor layer disposed on a top surface of the second Si_1-xGe_x semiconductor layer;

where the compound epitaxial oxide layer inhibits propagation of misfit dislocations from the first Si_1-xGe_x semiconductor layer into the second Si_1-xGe_x semiconductor layer and from the second Si_1-xGe_x semiconductor layer into the third semiconductor layer, where the misfit dislocations originate from nucleation centers formed by the implanted material in the first semiconductor layer.

10. The structure of claim 9, where the compound epitaxial oxide layer has a thickness in a range of about 10 nm to about 100 nm, or a thickness in a range of about 20 nm to about 50 nm, or a thickness of about 30 nm.

11. The structure of claim 9, where the third semiconductor layer is comprised of a strained Si layer.

12. The structure of claim 11, further comprising at least one NFET formed in the third semiconductor layer.

13. The structure of claim 9, where the third semiconductor layer is comprised of Si_1-xGe_x where the value of x in the third semiconductor layer is greater than the value of x in the first Si_1-xGe_x semiconductor layer.

14. The structure of claim 13, further comprising at least one PFET formed in the third semiconductor layer.

15. The structure of claim 9, where a Ge concentration in the second Si_1-xGe_x semiconductor layer is the same as a Ge concentration in the first Si_1-xGe_x semiconductor layer.

16. A structure, comprising:

a substrate having a top surface;

a first semiconductor layer disposed on the top surface of the substrate, the first semiconductor layer having a first unit cell geometry and comprising implanted ions;

a layer comprised of a metal-containing oxide disposed on the first semiconductor layer;

a second semiconductor layer disposed on the layer comprised of the metal-containing oxide, the second semiconductor layer having the first unit cell geometry;

a third semiconductor layer disposed on a top surface of the second semiconductor layer;

where the layer of metal-containing oxide has a second unit cell geometry that differs from the first unit cell geometry to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer and from the second semiconductor layer into the third semiconductor layer, where the misfit dislocations originate from nucleation centers formed by the implanted ions in the first semiconductor layer;

where the first semiconductor layer is comprised of Si_1-xGe_x, and where the third semiconductor layer is comprised of a layer of Si_1-xGe_x disposed on the top surface of the second semiconductor layer, where the value of x in the third semiconductor layer that is comprised of Si_1-xGe_x is greater than the value of x in the first semiconductor layer.

17. The structure of claim 16, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of a rare earth metal.

18. The structure of claim 16, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of at least one of cerium oxide (CeO₂), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), gadolinium oxide (Gd₂O₃), europium oxide (Eu₂O₃), terbium oxide (Tb₂O₃), a material ABO₃, where ‘

A’ and

‘

B’

may be any rare earth metal including lanthanum scandium oxide (LaScO₃) and lanthanum yttrium oxide (La_xY_1-x)₂O₃, samarium yttrium oxide (Sm_xY_1-x)₂O₃, lanthanum gadolinium oxide (La_xGd_1-x)₂O₃ and gadolinium europium oxide (Gd_xEu_1-x)₂O₃.

19. The structure of claim 16, where the first semiconductor layer is a strain relaxed layer comprised of Si_1-xGe_x.

20. The structure of claim 16, where the first unit cell geometry exhibits a diamond lattice crystal structure, and where the second unit cell geometry exhibits a cubic lattice crystal structure.