Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap

• US 9,685,372 B2
• Filed: 04/23/2015
• Issued: 06/20/2017
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hwang, Chien Ling, Liu, Chung-Shi, Wu, Yi-Wen, Tsai, Hui-Jung
• Primary Examiner(s): Slutsker, Julia
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US14/694,524
• Publication Number:
  US 20150228533A1
• Time in Patent Office: 789 Days
• Field of Search: 438613
• CPC Class Codes: C23C 14/34 Sputtering
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03826 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03831 involving a chemical process, e.g. etching the bonding area
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11622 : Photolithography
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1354 : Coating
• CPC Class Codes: H01L 2224/13565 : Only outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81024 : Applying flux to the bonding area
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81911 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.

Claims

1. A method of forming an integrated circuit device, the method comprising:

forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element;

forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and directly contacting a top surface of the first UBM layer;

etching the first UBM layer to remove a portion of the first UBM layer, wherein etching first UBM layer comprises removing the protection layer from an upper portion of the sidewalls of the conductive element; and

forming a cap layer over a top surface of the conductive element.

2. The method of claim 1, wherein forming the conductive element comprises:

forming a mask layer over the UBM layer;

patterning the mask layer to form an opening in the mask layer; and

forming the conductive element in the opening.

3. The method of claim 1, wherein the conductive element is formed by sputtering, printing, electro plating, electroless plating, electro-chemical plating or chemical vapor deposition.

4. The method of claim 1, wherein etching the second UBM layer comprises a wet etching process.

5. The method of claim 1, wherein forming the protection layer comprises forming the protection layer having a thickness ranging from about 500 angstroms to about 10,000 angstroms.

6. The method of claim 1, wherein forming the protection layer comprises forming the protection layer comprising at least one layer of a dielectric material.

7. The method of claim 1, further comprising etching the protection layer to expose the portion of the first UBM layer.

8. The method of claim 7, wherein etching the protection layer comprises removing the protection layer from the top surface of the conductive element.

9. The method of claim 1, wherein the first UBM layer is etched using a dry etching process.

10. The method of claim 1, wherein forming the cap layer comprises forming the cap layer over the upper portion of the sidewalls of the conductive element.

11. The method of claim 1, wherein removing the protection layer from the upper portion of the sidewalls comprises exposing the upper portion of the sidewalls of the conductive having a length ranging from about 2 microns (μ

m) to about 8 μ

m.

12. The method of claim 1, further comprising bonding the conductive element to a second substrate.

13. The method of claim 12, wherein bonding the conductive element to the second substrate comprises reflowing a solder layer between the conductive element and the second substrate, and the cap layer is between the conductive element and the solder layer.

14. A method of forming an integrated circuit device, the method comprising:

plating a conductive element over a first substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

depositing a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer, wherein the protection layer exposes an upper portion of the sidewalls of the conductive element;

forming a cap layer over a top surface and the upper portion of the sidewalls of the conductive element; and

bonding the conductive element to a second substrate using a solder layer, wherein the cap layer is between the conductive element and the solder layer.

15. The method of claim 14, wherein bonding the conductive element to the second substrate comprises bonding the conductive element to a contact pad or a conductive trace.

16. The method of claim 14, wherein plating the conductive element comprises plating a copper-containing material.

17. The method of claim 14, further comprising etching the first UBM layer using the protection layer over the sidewalls of the conductive element as a mask.

18. The method of claim 14, wherein plating the conductive element comprises:

forming a mask layer over a top surface of the second UBM layer;

patterning the mask layer to form an opening; and

plating the conductive element in the opening.

19. A method of forming an integrated circuit device, the method comprising:

plating a conductive element over a first substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

depositing a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer;

etching the first UBM layer using the protection layer as a mask, wherein etching the first UBM layer comprises removing the protection layer from an upper portion of the sidewalls of the conductive element;

forming a multi-layered cap layer over a top surface and the upper portion of the sidewalls of the conductive element; and

bonding the conductive element to a second substrate using a solder layer, wherein the cap layer is between the conductive element and the solder layer.

20. The method of claim 19, wherein bonding the conductive element to the second substrate comprises bonding the conductive element to a contact pad or a conductive trace.