Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate
First Claim
1. A three-dimensional (3D) semiconductor device comprising:
- a stack structure comprising electrodes that are vertically stacked on a substrate;
a channel structure coupled to the electrodes to constitute a plurality of memory cells that are three-dimensionally arranged on the substrate, the channel structure comprising;
first vertical channels and second vertical channels that penetrate the stack structure; and
a first horizontal channel that is under the stack structure and that laterally connects the first vertical channels and the second vertical channels to each other;
a second horizontal channel that is connected to a sidewall of the first horizontal channel of the channel structure, the second horizontal channel having a first conductivity type; and
conductive plugs that are on top ends of the second vertical channels, the conductive plugs having a second conductivity type.
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Accused Products
Abstract
A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.
44 Citations
20 Claims
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1. A three-dimensional (3D) semiconductor device comprising:
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a stack structure comprising electrodes that are vertically stacked on a substrate; a channel structure coupled to the electrodes to constitute a plurality of memory cells that are three-dimensionally arranged on the substrate, the channel structure comprising; first vertical channels and second vertical channels that penetrate the stack structure; and a first horizontal channel that is under the stack structure and that laterally connects the first vertical channels and the second vertical channels to each other; a second horizontal channel that is connected to a sidewall of the first horizontal channel of the channel structure, the second horizontal channel having a first conductivity type; and conductive plugs that are on top ends of the second vertical channels, the conductive plugs having a second conductivity type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A three-dimensional (3D) semiconductor device comprising:
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a stack structure that extends in a first direction and that includes a plurality of electrodes that are vertically stacked on a substrate; first vertical channels and second vertical channels that penetrate the stack structure; a first horizontal channel that extends in the first direction under the stack structure and that connects the first vertical channels and the second vertical channels to each other; a second horizontal channel that extends in the first direction to contact both sidewalls of the first horizontal channel and has a first conductivity type; and conductive plugs that are on top ends of the second vertical channels, the conductive plugs having a second conductivity type that different from the first conductivity type. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification